Dynamic Partial Reconfiguration of FPGA [Time-multiplex Silicon Resources on the Fly] Dr. Tassadaq Hussain www.tassadaq.ucerd.com Instructor: Dr. Rehan Ahmed [rehan.ahmed@seecs.edu.pk]

Configuration Memory Layer How is FPGA Programmed ? Think of an FPGA as two layered device: Configuration memory layer Logic layer Configuration memory controls function computed on logic layer (Re)Configuration Full Reconfiguration Partial Reconfiguration [PR] Dynamic PR Configuration Memory Layer Logic Layer

Dynamic Partial Reconfiguration (DPR) Dynamic:on the fly Partial:a portion of the FPGA Reconfiguration:configure again Program a Portion of the Chip; While the rest is in operation = Function A1 Function B1 Function C1 Full Bit File Function C2 Function B2 Function A2 Function A3 Configuration Port Partial Bit Files Configuration Port or ICAP

Benefits of Dynamic Partial Reconfiguration Partial Reconfiguration enables: System Flexibility Perform more functions while maintaining base design Size and Cost Reduction Time-multiplex the hardware to require a smaller FPGA Power Reduction Parts of the system not in use are swapped out

Example: Network Switch With Partial Reconfiguration Without Partial Reconfiguration

Example: Autovision Processor Region to enhance contrast Shape Engine Tunnel Engine Cont/Edge Engine Taillight Engine Optical Flow PPC Highway X X Tunnel entrance X X X Inside Tunnel X X Urban environment X X Mutually Exclusive Driving Conditions: Daytime vs. Nighttime: Detection of feature points (corners at day time) vs. Detection of taillights at nighttime Driving direction: backward vs. forward driving, different algorithms for front-and rear camera Different velocities: optical flow algorithm for motion detection during driving (highway), background subtraction when car is standing still (urban environment) Different weather conditions: fog, sun, snow, rain etc. Dynamic partial reconfiguration used to cope with that problem Situation adaptive system for driver assistance

Example: Autovision Processor Region to enhance contrast Shape Engine Tunnel Engine Cont/Edge Engine Taillight Engine Optical Flow PPC Highway X X Tunnel entrance X X X Inside Tunnel X X Urban environment X X SDRAM TunnelE. I/O PPC1 PPC0 Video IF TaillightE. PLB EdgeEng SChoappreoEc0ng ECdogperEocn1g ICAP MEM IF SEhdagpeeEEnngg Virtex II Pro FPGA Coprocessor Configurations

FPGA-based DPR-Platform

Components of DPR Architecture Ingredients of Dynamic Partial Reconfigurable System ICAP: Internal Configuration Access Port [A Door to Configuration Memory] PLB: Processor Local Bus [A Highway for Information Travelling] PR Region: Partial Reconfiguration Region [An Area reserved for partial configurations] I/O PPC1 PPC0 IP Block PLB Engine 2 Engine 2 Engine 1 PR Region Engine 2 Engine 1 ICAP MEM IF Engine 1 Virtex II Pro FPGA External Memory (SDRAM, CF etc)

Model-based Performance Evaluation

We want “Model-Based” performance evaluation, Problem Statement Reconfiguration Time: Overhead Reconfigurable Systems suffer from Reconfiguration Overhead Reconfiguration Time ~ not known till implementation Important for Safety Critical Systems Performance Trends different design parameters = several candidates implement on the chip and take measurements ~ requires months We want “Model-Based” performance evaluation, *No Implementation*

Objective Develop a Generalized Model What do we want from our model? That Mimics the behaviour of Reconfigurable Systems That can be applied across different types of designs What do we want from our model? To predict reconfiguration time (RT) early in the design cycle So I can see if I can meet the deadlines To gain insight into high-level design trends So I can evaluate different design candidates quickly

Methodology Queueing Theory

Our-Approach: Modeling PR using Queueing Theory Model features mapped to a Queueing Network Multi-Class Queueing Networks Solve using Two ways Simulation-Based Analytical-Based

Two-Phase Example

Comparison with Measured Value Estimated results from QT Model were generated and compared with measured values: Measured Estimated TP(MB/s) 90 89.7 RT(ms) [BS size:150 KB] 1.66 1.67

ICAP Trends Bus Becomes the New Bottleneck! ICAP Utilization ICAP Width PR Bus Utilization

ICAP Trends ICAP affects PR and non-PR traffic PR Throughput ICAP Width Non-PR Throughput

BRAM Trends

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