Kejia Li, Yang Fu University of Virginia

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Presentation transcript:

Low Power Lookup Table Using Power Gating and Forward Body Biasing Techniques Kejia Li, Yang Fu University of Virginia Department of Electrical and Computer Engineering Charlottesville, VA 22904

Outline Introduction System components Simulation results Summary Mux structure Well Driver for FBB Power gating circuitry Output buffer Level converter Simulation results High power mode 1 High power mode 2 Low power mode Sleep mode Summary

Introduction Low-power design techniques We choose LUT as Power gating Body biasing Gate biasing Dual-VDD Dual-Vt … We choose LUT as the base line device

System Components Input Buffer Mux Output Buffer SRAM configuration bits Level Converter Control Signal Bus Output Well Driver Power Gating Selector

System Components

Mux Structure We use high Vt devices (NMOS_VTG) in the mux together with forward body biasing.

The Well Driver Generate the body bias required for FBB ~0.64V in our design A trade-off between power and delay

Power Gating Circuitry High power mode: both PMOS and NMOS are on Low power mode: PMOS off, NMOS on  reduced VVDD Sleep Mode: PMOS off, NMOS off Header circuit Mode selection circuit

Output Driver Use a PMOS keeper to restore the logic level after the mux

Level Converter Used in the low power mode operation Reduced swing signal  Full swing signal Restore logic level to prevent leakage in subsequent stages.

High Power Mode 1 FBB on / Power gating: PMOS on, NMOS on Energy per switch: 148 fJ Static power: 450 nW Delay: 296 ns

High Power Mode 2 FBB off / Power gating: PMOS on, NMOS on Energy per switch: 148 fJ Static power: 370 nW Delay: 311 ns

Low Power Mode FBB on / Power gating: PMOS off, NMOS on Energy per switch: 101 fJ Static power: 280 nW Delay: 556 ns

Sleep Mode FBB off / Power gating: PMOS off, NMOS off Static power: 84 nW

Summary We have designed a low power lookup table using power gating and forward body biasing techniques. Four different operation modes are available, depending on the power/delay requirement. Future work needed to optimize the performance (like reducing leakage).

The End Thank you!