ESE535: Electronic Design Automation

Slides:



Advertisements
Similar presentations
Penn ESE 535 Spring DeHon 1 ESE535: Electronic Design Automation Day 12: February 23, 2011 Routing 2 (Pathfinder)
Advertisements

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 11: March 4, 2008 Placement (Intro, Constructive)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 20: April 13, 2009 Placement II (Simulated Annealing)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 9: February 20, 2008 Partitioning (Intro, KLFM)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 2: January 23, 2008 Covering.
EDA (CS286.5b) Day 5 Partitioning: Intro + KLFM. Today Partitioning –why important –practical attack –variations and issues.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 21: April 15, 2009 Routing 1.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 19: April 9, 2008 Routing 1.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 16: March 23, 2009 Covering.
EDA (CS286.5b) Day 7 Placement (Simulated Annealing) Assignment #1 due Friday.
Penn ESE525 Spring DeHon 1 ESE535: Electronic Design Automation Day 10: February 18, 2009 Partitioning 2 (spectral, network flow)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 8: February 13, 2008 Retiming.
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 4: January 28, 2015 Partitioning (Intro, KLFM)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 2: January 26, 2015 Covering Work preclass exercise.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 2: January 21, 2015 Heterogeneous Multicontext Computing Array Work Preclass.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 9: February 16, 2015 Scheduling Variants and Approaches.
Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 9: February 14, 2011 Placement (Intro, Constructive)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 24: April 18, 2011 Covering and Retiming.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 10: February 18, 2015 Architecture Synthesis (Provisioning, Allocation)
Modern VLSI Design 3e: Chapter 10 Copyright  1998, 2002 Prentice Hall PTR Topics n CAD systems. n Simulation. n Placement and routing. n Layout analysis.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 6: January 23, 2002 Partitioning (Intro, KLFM)
Penn ESE525 Spring DeHon 1 ESE535: Electronic Design Automation Day 6: February 4, 2014 Partitioning 2 (spectral, network flow)
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 10: February 6, 2002 Placement (Simulated Annealing…)
CSE 589 Part VI. Reading Skiena, Sections 5.5 and 6.8 CLR, chapter 37.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 23: April 20, 2015 Static Timing Analysis and Multi-Level Speedup.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 13: March 3, 2015 Routing 1.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 9: February 9, 2004 Partitioning (Intro, KLFM)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 10: February 16, 2011 Placement II (Simulated Annealing)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 6: January 30, 2013 Partitioning (Intro, KLFM)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 20: April 4, 2011 Static Timing Analysis and Multi-Level Speedup.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 15: March 13, 2013 High Level Synthesis II Dataflow Graph Sharing.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 11: February 25, 2015 Placement (Intro, Constructive)
CALTECH CS137 Fall DeHon 1 CS137: Electronic Design Automation Day 2: September 28, 2005 Covering.
CALTECH CS137 Winter DeHon 1 CS137: Electronic Design Automation Day 8: January 27, 2006 Cellular Placement.
CALTECH CS137 Fall DeHon 1 CS137: Electronic Design Automation Day 21: November 28, 2005 Routing 1.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 25: April 17, 2013 Covering and Retiming.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 5: January 31, 2011 Scheduling Variants and Approaches.
VLSI Physical Design Automation
ESE534: Computer Organization
ESE534 Computer Organization
CS137: Electronic Design Automation
ESE532: System-on-a-Chip Architecture
CS137: Electronic Design Automation
CS137: Electronic Design Automation
CS137: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE534: Computer Organization
ESE534: Computer Organization
ESE535: Electronic Design Automation
EE5780 Advanced VLSI Computer-Aided Design
ESE534: Computer Organization
ESE535: Electronic Design Automation
Topics Logic synthesis. Placement and routing..
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE534: Computer Organization
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
Presentation transcript:

ESE535: Electronic Design Automation Day 9: February 11, 2013 Placement (Intro, Constructive) Penn ESE535 Spring 2013 -- DeHon

Today 2D Placement Problem PartitioningPlacement Quadrisection Behavioral (C, MATLAB, …) RTL Gate Netlist Layout Masks Arch. Select Schedule FSM assign Two-level, Multilevel opt. Covering Retiming Placement Routing Today 2D Placement Problem PartitioningPlacement Quadrisection Refinement Penn ESE535 Spring 2013 -- DeHon

Placement Problem: Pick locations for all building blocks minimizing energy, delay, area really: minimize wire length minimize channel density Penn ESE535 Spring 2013 -- DeHon

Bad Placement How bad can it be? Area Delay Energy Penn ESE535 Spring 2013 -- DeHon

Preclass Channel Widths Channel Width for Problem 1? Penn ESE535 Spring 2013 -- DeHon

Preclass Channel Widths Channel Width for Problem 2? Penn ESE535 Spring 2013 -- DeHon

Bad: Area All wires cross bisection O(N2) area good: O(N) Penn ESE535 Spring 2013 -- DeHon

Delay How bad can delay be? Penn ESE535 Spring 2013 -- DeHon

Delay How good can delay be? Penn ESE535 Spring 2013 -- DeHon

Bad: Delay All critical path wires cross chip Delay =O(|PATH|*2*Lside) [and Lside is O(N)] good: O(|PATH|* Lg) compare 10ps gates to many nanoseconds to cross chip Penn ESE535 Spring 2013 -- DeHon

Clock Cycle Radius Radius of logic can reach in one cycle (45 nm) Few hundred PEs Chip side 600-700 PE 400-500 thousand PEs 100s of cycles to cross Penn ESE535 Spring 2013 -- DeHon

Bad: Energy All wires cross chip: Good: O(Lside) long  O(Lside) capacitance per wire Recall AreaO(N2) So Lside  O(N) O(N) wires  O(N2) capacitance Good: O(1) long wires  O(N) capacitance Penn ESE535 Spring 2013 -- DeHon

Manhattan Penn ESE535 Spring 2013 -- DeHon

Manhattan Distance Horizontal and Vertical Routing: Manhattan distance |Xi-Xj|+|Yi-Yj| Contrast: Euclidean distance Penn ESE535 Spring 2013 -- DeHon

Distance Can we place everything close? Penn ESE535 Spring 2013 -- DeHon

Illustration Consider a complete tree Logical circuit depth? nand2’s, no fanout N nodes Logical circuit depth? Circuit Area? Side Length? Average wire length between nand gates? (lower bound) Penn ESE535 Spring 2013 -- DeHon

“Closeness” Try placing “everything” close Penn ESE535 Spring 2013 -- DeHon

Alternate Wire Length Illustration Consider a cut width F(N) > N If optimally place all F(N) producers right next to bisection How many cells deep is the producer farthest from the bisection? ? Penn ESE535 Spring 2013 -- DeHon

Generalizing Interconnect Lengths Large cut widths imply long wires ? Penn ESE535 Spring 2013 -- DeHon

Placement Problem Characteristics Familiar NP Complete local, greedy not work greedy gets stuck in local minima Penn ESE535 Spring 2013 -- DeHon

Constructive Placement Penn ESE535 Spring 2013 -- DeHon

Basic Idea Partition (bisect) to define halves of chip minimize wire crossing Recurse to refine When get down to single component, done Penn ESE535 Spring 2013 -- DeHon

Adequate? Does recursive bisection capture the primary constraints of two-dimensional placement? Penn ESE535 Spring 2013 -- DeHon

Problems Greedy, top-down cuts Two-dimensional problem maybe better pay cost early? Two-dimensional problem (often) no real cost difference between H and V cuts Interaction between subtrees not modeled by recursive bisect Penn ESE535 Spring 2013 -- DeHon

Interaction Penn ESE535 Spring 2013 -- DeHon

Example Ideal split (not typical) “Equivalent” split ignoring external constraints Practically -- makes all H cuts also be V cuts Penn ESE535 Spring 2013 -- DeHon

Interaction Penn ESE535 Spring 2013 -- DeHon

Problem Need to keep track of where things are outside of current partition include costs induced by above …but don’t necessarily know where things are still solving problem Penn ESE535 Spring 2013 -- DeHon

Improvement: Ordered Order operations Keep track of existing solution Use to constrain or pass costs to next subproblem B A Penn ESE535 Spring 2013 -- DeHon

Improvement: Ordered Order operations Keep track of existing solution Use to constrain or pass costs to next subproblem Flow cut use existing in src/sink A nets = src, B nets = sink S A B T Penn ESE535 Spring 2013 -- DeHon

Improvement: Ordered Order operations Keep track of existing solution Use to constrain or pass costs to next subproblem Flow cut use existing in src/sink A nets = src, B nets = sink FM: start with fixed, unmovable nets for side-biased inputs S A B T Penn ESE535 Spring 2013 -- DeHon

Improvement: Constrain Partition once Constrain movement within existing partitions Account for both H and V crossings Partition next (simultaneously work parallel problems) easy modification to FM Penn ESE535 Spring 2013 -- DeHon

Constrain Partition C A B D Solve AB and CD concurrently. Penn ESE535 Spring 2013 -- DeHon

Improvement: Quadrisect Solve more of problem at once Quadrisection: partition into 4 bins simultaneously keep track of costs all around Penn ESE535 Spring 2013 -- DeHon

Quadrisect Modify FM to work on multiple buckets k-way has: k(k-1) buckets |from||to| quad 12 reformulate gains update still O(1) Penn ESE535 Spring 2013 -- DeHon

Quadrisect Cases (15): (1 partition)  4 (2 part)  6 = (4 choose 2) Penn ESE535 Spring 2013 -- DeHon

Recurse Keep outside constraints Problem? What can we do? (cost effects) Problem? Don’t know detail place What can we do? Model as at center of unrefined region Penn ESE535 Spring 2013 -- DeHon

Option: Terminal Propagation Abstract inputs as terminals Partition based upon Represent cost effects on placement/refinement decisions Penn ESE535 Spring 2013 -- DeHon

Option: Refine Keep refined placement Use in cost estimates Penn ESE535 Spring 2013 -- DeHon

Problem Still have ordering problem What is the problem? Earlier subproblems solved with weak constraints from later (cruder placement estimates) Solved previous case by flattening Why might not be satisfied with that? In extreme give up divide and conquer Alternative? Penn ESE535 Spring 2013 -- DeHon

Iterate After solve later problems “Relax” solution Solve earlier problems again with refined placements (cost estimates) Repeat until converge Penn ESE535 Spring 2013 -- DeHon

Iteration/Cycling General technique to deal with phase-ordering problem what order do we perform transformations, make decisions? How get accurate information to everyone Still basically greedy Penn ESE535 Spring 2013 -- DeHon

Refinement Relax using overlapping windows Deal with edging effects Huang&Kahng claim 10-15% improve cycle overlap Penn ESE535 Spring 2013 -- DeHon

Possible Refinement Allow unbalanced cuts most things still work just distort refinement groups allowing unbalance using FM quadrisection looks a bit tricky gives another 5-10% improvement Penn ESE535 Spring 2013 -- DeHon

Runtime Each gain update still O(1) O(1) iterations expected (bigger constants) so, FM partition pass still O(N) O(1) iterations expected assume O(1) overlaps exploited O(log(N)) levels Total: O(N log(N)) very fast compared to typical annealing (annealing next time) Penn ESE535 Spring 2013 -- DeHon

Quality: Area [Huang&Kahng/ISPD1997] Gordian-L: Analytic global placer DOMINO: network flow detail Quality: Area [Huang&Kahng/ISPD1997] Penn ESE535 Spring 2013 -- DeHon

Quality: Delay Weight edges based on criticality Periodic, interleaved timing analysis Penn ESE535 Spring 2013 -- DeHon

Uses Good by self Starting point for simulated annealing speed convergence With synthesis (both high level and logic) get a quick estimate of physical effects (play role in estimation/refinement at larger level) Early/fast placement before willing to spend time looking for best For fast placement where time matters FPGAs, online placement? Penn ESE535 Spring 2013 -- DeHon

Summary Partition to minimize cut size Additional constraints to do well Improving constant factors Quadrisection Keep track of estimated placement Relax/iterate/Refine Penn ESE535 Spring 2013 -- DeHon

Big Ideas: Potential dominance of interconnect Divide-and-conquer Successive Refinement Phase ordering: estimate/relax/iterate Penn ESE535 Spring 2013 -- DeHon

Admin Assignment 3 out No Office Hours Tuesday No class Wednesday Reading for next Monday Online (JSTOR): classic paper on Simulated Annealing Drop Day is Friday …I will try to make some grading progress while I travel… Penn ESE535 Spring 2013 -- DeHon