IDEA 2016 I nvestigating D ataflow in E mbedded computing A rchitecture Process Networks for Reactive Streaming with Timed Automata Implementation P. Poplavko, D. Socci, R. Kahil, M. Bozga, S. Bensalem Verimag Lab (CNRS, University of Grenoble), France

Peter Poplavko / Verimag, Grenoble Motivation Streaming frameworks, e.g. EU CompSoC based on dataflow MoCs - no timing-dependent actions, no deadlines and periods Reactive-control frameworks e.g. ONERA Prelude, ESA TASTE based on synchronous-languages + real-time systems analysis - overdesigned in terms of timing constraints Tradeoff between them required in certain application domains Proposed MoC: Fixed Priority Process Network 14-Apr-19 Peter Poplavko / Verimag, Grenoble

Example: Flight Management System SensorInput 200ms AnemoConfig 2 per200ms GPSConfig IRSConfig DopplerConfig HighFreqBCP LowFreqBCP 5000ms MagnDeclin 1600ms BCPConfig Performance 1000ms MagnDeclinConfig 5 per1600ms PerformanceConfig 5 per1000ms AnemoData GPSData IRSData DopplerData PerformanceData BCP Data relative functional priority 14-Apr-19 Peter Poplavko / Verimag, Grenoble

Timed Automata Implementation Ctrller TTS Cycle TTS Frame f1 TTS Frame f3 core 0: BIP RTE + middleware components TTS Frame MailBx BlacBrd core 1..15: process-to-core mapping scheduler components in BIP application FPPN MoC components in BIP core 1: core 2: `migrating’ components:  1  2  3  4  6 Per. Server  5 RTE engine 2 4 1 3 5 6 14-Apr-19 Peter Poplavko / Verimag, Grenoble

Peter Poplavko / Verimag, Grenoble Welcome to my poster! 14-Apr-19 Peter Poplavko / Verimag, Grenoble