Self Introduction & Progress Report Chester Liu 2013/6/21

Self Introduction Name 劉威孝 (Chester Liu) Education Work experience High school: WuLing (2001-2004) Undergrad: EE, NTHU (2004-2008) Graduate: GIEE, NTU (2008-2010) Advisor: Prof. Chien-Mo Li Thesis: Placement Optimization of Flexible TFT Digital Circuits Work experience Digital IC engineer, MediaTek (2010-2013) Smart phone platform team (memory group) DRAM integration, performance verification FPGA integration, simulation & synthesis environment Design AXI 64/128 pack/unpack, cross clock-domain protocol converter Misc. platform architecture, debug

Self Introduction (fun part) Work experience (contd.) Year-end banquet staff, MediaTek Large poster design Hobby Web design LaDS, NTU Ultrafast Photonics Lab., NTHU GUNPLA LEGO

Current System Architecture Key components Camera sensor Set sensor configuration through I2C Sensor output converted by VIP controller then written to DRAM by VIP controller internal DMA No direct connection to FPGA DVC encoder Software DVC encoder running on ARM11 Get raw data from DRAM Write encoded result to DRAM WiFi module Connected using USB Still need MAC+PHY and SW stack even if it’s connected to FPGA

Proposed System Architecture (Stage 1) Before HW DVC encoder test chip back Key components Same camera sensor (Aptina MT9V125) Camera controller convert sensor output for HW DVC encoder to use Different WiFi module (Redpine RS-9110) Self contained 802.11 module with networking stack Host interface: UART or SPI UART selected at this stage for its simplicity System controlled by a simple FSM Hardware specification Xilinx XC5VLX330 capacity 207360 LUTs/FFs, 1296KB block RAM Redpine RS-9110 host side throughput UART ~1.3Mbps (according to customer service e-mail reply) SPI ~8Mbps (according to datasheet)

Proposed System Architecture (Stage 2) After HW DVC encoder test chip back Key components Same WiFi module Use SPI host interface for higher throughput Control is more complicated than using UART Altera EP4CE22 Reduce system cost and form factor Nios II soft core processor Replace the simple FSM Fetch code from on-chip SRAM Hardware specification Altera EP4CE22 capacity 22320 LEs, 74.25KB embedded memory

To-Do Study Board inspection Camera sensor output protocol HW DVC encoder input/output protocol WiFi module usage Board inspection How to connect camera and WiFi module to FPGA I/O voltage compatibility