Team Awesome += 5 PICo Design Presentation Douglas Grosvenor, Terence Crumbley, Jeffrey Gaither

Overview Background Design Testing Metrics Questions

Background PICo SRAM Low power High speed 1 Mb Long lifetime Metric: (Total Power)^2 * Delay * Area High speed 64 kb Encryption/Compression Metric: (Total Power) * Delay^2 * Area

Design 32bit words 2 words per row 64 rows per block 4096 bits per block 16 blocks array

Array Diagram

Block Diagram

Bitcell Layout

Design Cont’ Read/Write Signal System Pulse Generator WL Generator Decoder

Read/Write Signal System

Pulse Generator

Pulse Signal Blue – Input signal Orange – Output signal

Word Line Generator

6 to 64 Decoder

Testing Approach One Approach Two Corner Simulation Four Bitcells RC Based on extracted layout Approach Two Full word, read/write Active/Inactive Different words

Simulation of Read/Write

Analysis Metrics Area*(Delay^2)*Power Delay Power Area metric 1.75e11 mW*ns2*µm2 bitcell area 218.4µm2 total area 28M µm2 read power 111.43mW write power 72.39mW total power 207.005mW read delay 5.5ns write delay 2.5ns total delay

Conclusion Background Design Testing Metrics

Questions?

Sense Amp

2 to 4 Decoder

2 to 4 Enable Dec.

Bitcell

Simulation

Simulation cont’d

Simulation cont’d

Problems Sense Amp Wiring problems