Status of CC-PC Evaluation Board Beat Jost Cern / EP

Motivation To build a test board to demonstrate the applicability of the CC-PCs to controlling electronics board measure the impact of noise induced by the CC-PC on analog electronic circuits to learn how to interface the CC-PC to electronics boards I2C generation/usage JTAG generation/usage most suitable parallel bus structure reset of CC-PC without interference on rest of board finally provide a design block that board designers can implement

Board Block Diagram

Detail of CC-PC and Glue Logic Idea of the “glueboard” is to take all signals of the CC-PC 1-1 and generate whatever signals are needed on the 3rd connector Pros complete independence of the pinout of the CC-PC standard board easier maintenance Cons Potentially board space slightly higher cost potentially more layers on PCB to bring signals over

LHCb Specific Interface 40 MHz clock Reset Interrupt line Power, Ground Parallel Bus 32 Address/Data lines multiplexed 11 Control Lines 4 x I2C (for the moment only one being driven) 2 x JTAG (for the moment only one being driven) Parallel Port Ethernet (10/100 base T) RS232

Time Scale PC Board MachZ-based smart modules January->March design finished before Xmas almost all components are in hand (ADC and Phos missing) plastic in January MachZ-based smart modules prototypes running and being tested at Digital Logic mass production starting February 2001 we hope to get one or two samples soon January->March testing functionality measure noise testing RESET behavior