Compiled by Dr. N.Shanmugasundaram, HOD, ECE Dept, SECE. Intel 8051 Compiled by Dr. N.Shanmugasundaram, HOD, ECE Dept, SECE. Dr.NSS/ECE April 12, 2019

What is microcontroller? Intel 8051 - Introduction What is microcontroller? Microcontroller is a single IC which contains the CPU along with peripherals like memory, serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC, etc. CPU On-chip ROM RAM Timers I/O Ports ADC, etc. Dr.NSS/ECE April 12, 2019

Intel 8051 - Introduction Features of Intel 8051 40 Pin DIP chip operating at 12 MHz Data bus size = 8-bit Address bus size = 16-bit (Memory capacity = 216 = 64 KB) On-chip RAM = 128 Bytes On-chip ROM = 4 KB 2 In-built Timers (16-bits each) 4 I/O Ports ( 8-bit each) 1 Serial port (Full Duplex) Interrupt Sources = 6 ( inclusive of two H/w interrupts – INT0, INT1) Register organization 8-bit register = A, B, SP, 4 x Register banks (with 8 registers in each bank) 16-bit register = PC, DPTR Special Function Registers (SFRs). Dr.NSS/ECE April 12, 2019

Intel 8051 – Pin Diagram & Description Dr.NSS/ECE April 12, 2019

Intel 8051 – Architecture block diagram Dr.NSS/ECE April 12, 2019

Intel 8051 – Special Function Register Dr.NSS/ECE April 12, 2019

Intel 8051 – PSW : Program Status Word (Flag Register) Dr.NSS/ECE April 12, 2019

Intel 8051 – Memory Organization PROGRAM MEMORY EA (External Access) is the pin that informs the microcontroller about the usage of external memory. EA = GND External memory is ONLY used EA = VCC No External memory is connected DATA MEMORY Dr.NSS/ECE April 12, 2019

Intel 8051 – Structure of Internal RAM Dr.NSS/ECE April 12, 2019

Intel 8051 – I/O Ports & Pin Structure A pin of any I/O port of 8051 has following 3 major components.. i) Latch ii) Driver transistor iii) Tri-state buffer (2 Nos) The difference in pin structure of Port 0 and Ports 1, 2 & 3 is internal pull-up resistor in driver transistor. The control signals for the I/O port are Read Latch, Write Latch and Read Pin. The instruction that reads the pin of an I/O port is MOV A, P1 The instruction that reads the latch of an I/O port is ANL A, P1 Dr.NSS/ECE April 12, 2019

Intel 8051 – Timers and Counters Timers / Counters in 8051 are used to generate time delay for timed operations for counting the occurrence of external events. The two 16-bit registers for Timer/Counter operations in 8051 are, Timer 0 Timer 1 The two 8-bit Timer control registers in 8051 are, TMOD TCON Dr.NSS/ECE April 12, 2019

Intel 8051 – Timers and Counters Timer Mode Control Register (TMOD): Dr.NSS/ECE April 12, 2019

Intel 8051 – Timers and Counters Timer Control Register (TCON): Dr.NSS/ECE April 12, 2019

Intel 8051 – Timers and Counters Timer mode: In this mode, the timer register is used to generate the time delay using the clock signal is applied to the processor. The register is incremented after every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. Dr.NSS/ECE April 12, 2019

Intel 8051 – Timers and Counters Counter mode: In this mode, the timer register is used to count the event using external pulses supplied through counter inputs T0 & T1. Dr.NSS/ECE April 12, 2019

Intel 8051 – Serial Communication Types of Serial communication There are two main types of Serial communication are (i) Synchronous and (ii) Asynchronous serial communications. The most commonly used is Asynchronous serial communications. The bit format for asynchronous data transmission in UART is, Dr.NSS/ECE April 12, 2019

Intel 8051 – Serial Communication The serial communication in 8051 is carried out using two SFR registers, * SCON * SBUF SCON is used to control and set the mode of serial communication. SBUF is used to dump the data before serial transmission and hold data after serial reception. Dr.NSS/ECE April 12, 2019

Intel 8051 – Serial Communication Serial Port Control Register (SCON): SCON register is used to control the serial communication between 8051 and any external peripherals. Dr.NSS/ECE April 12, 2019

Intel 8051 – Serial Communication Baud rate Generation: Based on the baud rate needed for serial communication, the timer register TH1 is loaded with values as follows. Baud rate Frequency Divisor Hex value loaded in TH1 register 9600 03 FD 4800 06 FA 2400 12 EE 1200 24 DC Dr.NSS/ECE April 12, 2019

Intel 8051 – Interrupts The six sources of interrupt in 8051 are as follows.. RST - Reset 8051 INT0 - Hardware Interrupt – I INT1 - Hardware Interrupt – II TF0 - Timer-0 overflow Interrupt flag TF1 - Timer-1 overflow Interrupt flag TI/RI - Serial port Interrupts All above interrupts are disabled upon reset, except RST. The interrupts are enabled and its priority is set by using two 8-bit SFR registers IE & IP. Dr.NSS/ECE April 12, 2019

Intel 8051 – Interrupts Interrupt Enable Register (IE): The IE register is used to enable/disable the interrupts of 8051. The interrupts are recognized by the controller only if they are enabled. The format of IE register is, Dr.NSS/ECE April 12, 2019

Intel 8051 – Interrupts Interrupt Priority The 8051 has five interrupts, excluding RST. The normal priority of these interrupts from highest to lowest are INT0 - External interrupt-0 TF0 - Timer-0 overflow interrupt INT1 - External interrupt-1 TF1 - Timer-1 overflow interrupt TI/RI - Serial Port interrupt. Dr.NSS/ECE April 12, 2019

Intel 8051 – Interrupts The IP register can be programmed to alter the default priority of any of the interrupt. The priority of any interrupt can be set as highest, by making the priority bit of that particular interrupt programmed as ‘1’. The priority is set to normal, when the priority bit of that interrupt is reset to ‘0’. The format of IP register is, Dr.NSS/ECE April 12, 2019

Programming 8051 ADDRESSING MODES: The 8051 has the following types of addressing. Immediate Addressing - Eg. MOV A, #6CH Direct Addressing - Eg. MOV A, 07 H Register Addressing - Eg. MOV R2, A Register Indirect Addressing - Eg. MOV A, @Ri Indexed Addressing - Eg. MOVX A, @A+DPTR Dr.NSS/ECE April 12, 2019

Programming 8051 INSTRUCTION SET : The instructions can be classified into the following five groups. Data transfer instructions Arithmetic instructions Logical instructions Branching instructions Single bit instructions Dr.NSS/ECE April 12, 2019

MOV A, Source MOV Rn, Source MOV Direct, Source MOV indirect, Source MOV DPTR, … MOVC A, … MOVX A, … PUSH, POP (Stack) Exchange A, … Dr.NSS/ECE April 12, 2019

ADD A, II Source ADDC A, II Source SUBB A, II Source INC Source DEC Source INC DPTR MUL AB (Multiply) DIV AB (Division) Dr.NSS/ECE April 12, 2019

AND A, II Source OR A, II Source X-OR A, II Source Clear Complement Rotate Swap Dr.NSS/ECE April 12, 2019

CALL Subroutine Return Unconditional Jump Conditional Jump Compare & Jump Decrement & Jump No Operation Dr.NSS/ECE April 12, 2019

Clear Bit Set Bit Complement Bit AND Bits OR Bits MOV Bit Dr.NSS/ECE April 12, 2019

Intel 8051 – LCD Interface The status of RS, R/W and E pins for data & command operations in LCD. Pin / Operation Command Data RS (Register Select) 1 R/W (Read/Write) 0 – Write 1 – Read E (Enable) H-to-L Pulse Dr.NSS/ECE April 12, 2019

Intel 8051 – LCD Interface Two methods for sending data / command to LCD I Method: Using predefined time delay II Method: By Checking the busy flag Dr.NSS/ECE April 12, 2019

Intel 8051 – Keyboard Interface The rows and columns of the matrix keyboard (eg., 4 x 4) is connected to two ports of the microcontroller (port 1 as output port and port 2 as input port). Dr.NSS/ECE April 12, 2019

Intel 8051 – Keyboard Interface Keyboard Scanning Process: All rows are first grounded and all columns are checked for key pressing. If a key in any column found pressed; then rows are resetted and rows are now grounded one by one and all columns are again checked. When the exact row and column of key pressed in found and scan code for corresponding key is generated and sent to the microcontroller. (Explain the Flow Chart) Dr.NSS/ECE April 12, 2019

Intel 8051 – ADC Interface Dr.NSS/ECE April 12, 2019

Intel 8051 – DAC DAC INTERFACE DAC stands for Digital to Analog Converter. Types of DAC : 1) Average Weighted Resistor method 2) R/2R ladder Network (most widely used) Resolution: The change in output for the minimum change in input. (R=Vref / 2n) Conversion Time: It is the time taken to completely convert the digital signal into a analog signal in the D/A converter and the minimum conversion time in DAC0808 is 110µS. R/2R ladder network method is most commonly used in DAC and output of a DAC is given by, Output of a DAC is generally in current (I) form and it is converted into voltage form with the help of a resistor. Dr.NSS/ECE April 12, 2019

Intel 8051 – DAC Interface Dr.NSS/ECE April 12, 2019