ADS54J66 Test

ADS54J66 Test Setup: Single tone is given as input to the device. Test conditions: Fs = 500Msps External CLK @ 12dBm input to splitter, output to J6 and J12 on ADC EVM IF = 96MHz Bypass mode LMFS = 4421 Move C47 to R35 Move C48 to R39

ADS54J66EVM Setup

Load LMK file shown below.

On LMK04828 Clock Outputs tab, set CLK 0 divider to 2 and CLK 2 divider to 1. Make sure CLK 2 DCLK source is as shown below.

Set SYSREF Divider = 128

Press the ADS54J66EVM board reset then load the ADC config file shown below.

CHD, Fin = 96MHz