Advanced Digital Design Organisation A. Steininger / TU Wien

„Key Data“ Elective Subject Master CE Elective Subject PhD course Type: VU 6.0 SWS (6 ETCS) Lecturers Andreas Steininger Jakob Lechner Robert Najvirt Thomas Polzer A. Steininger / TU Wien

Course Context Bachelor Master Digital Design VO 4. Digital Design & Comp Arch. LU 5. Hardware-Modelling 5. Master HW/SW-Codesign WT Advanced Digital Design WT Scientific Project Informatikpraktikum Master Thesis A. Steininger / TU Wien

Course Contents Metastability: GALS Asynchronous Design phenomenon, MTBU-equation & derivation measurement of MTBU + related parameters synchronizers GALS levels of synchronity data exchange via synchronizer stoppable clocking, MUTEX Asynchronous Design Bundled Data & QDI Data Flow Structures („Token Game“) Control Structures (STG) Design entry & Design Automation A. Steininger / TU Wien

Course Structure Lecture (25%): Homeworks / Exercises (25%): standard lectures 10 units, 3 topical blocks Homeworks / Exercises (25%): submission of written elaboration discussion in the group, 3 units Design Projects submission of solution discussion with advisor / group A. Steininger / TU Wien

Homeworks/Exercises typically 3-5 problems assigned solutions to be worked out individually submission of pdf with solution (minimum level of optical attractiveness applies) to steininger@ecs.tuwien.ac.at submission no later than the day before the discussion, 12:00 noon A. Steininger / TU Wien

Design Problems typically 1-2 problems assigned solutions to be worked out in groups of 3 submission of pdf with solution (minimum level of optical attractiveness applies) to steininger@ecs.tuwien.ac.at submission no later than the day before the discussion, 12:00 noon A. Steininger / TU Wien

Course Material Lecture Slides web Homework Problems web Design Problems web Collection of Solutions web ? Textbooks Jens Sparso and Steve Furber web (free) Principles of Asynchronous Circuit Design – A Systems Perspective Kluwer http://www2.imm.dtu.dk/~jsp/ David Kinniment Synchronization and Arbitration in Digital Systems Wiley A. Steininger / TU Wien

Grading quality of submitted homeworks quality of submitted designs written examination (Jan/Feb) contributions during the lectures during the discussions of homeworks through presentation of own solutions A. Steininger / TU Wien