Memories: RAM, ROM Advanced Testbenches ECE 545 Lecture 9 Memories: RAM, ROM Advanced Testbenches ECE 545 – Introduction to VHDL

Sources & Required Reading Volnei A. Pedroni, Circuit Design with VHDL Chapter 9.10, Memory Design Chapter 7.1, Constant Chapter 3.6, Records Chapter 11.6, Assert Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 14, starting from “Design Verification” ECE 545 – Introduction to VHDL

Generic Memories ECE 545 – Introduction to VHDL

Generic RAM (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------- ENTITY ram IS GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 256); -- # of words in the memory PORT (wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 to words-1; data_in: IN STD_LOGIC_VECTOR(bits -1 downto 0); data_out: OUT STD_LOGIC_VECTOR(bits - 1 downto 0) ); END ram; ECE 545 – Introduction to VHDL

Generic RAM – inferring LUT-based RAM (2) ARCHITECTURE LUT_based_ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits-1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS(clk) IF (rising_edge(clk)) THEN IF(wr_ena=‘1’) THEN memory(addr) <= data_in; END IF; END PROCESS; data_out <= memory(addr); END LUT_based_RAM; ECE 545 – Introduction to VHDL

Report from Synthesis (1) Mapping to part: xc3s50vq100-5 Cell usage: MUXF5 8 uses RAM64X1S 32 uses LUT3 20 uses RAM/ROM usage summary Single Port Rams (RAM64X1S): 32 Mapping Summary: Total LUTs: 148 (9%) ECE 545 – Introduction to VHDL

Report from Implementation (1) Target Device : xc3s50 Target Package : vq100 Target Speed : -5 Design Summary -------------- Logic Utilization: Number of 4 input LUTs: 20 out of 1,536 1% Logic Distribution: Number of occupied Slices: 74 out of 768 9% Number of Slices containing only related logic: 74 out of 74 100% Number of Slices containing unrelated logic: 0 out of 74 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 148 out of 1,536 9% Number used as logic: 20 Number used for 32x1 RAMs: 128 (Two LUTs used per 32x1 RAM) ECE 545 – Introduction to VHDL

CLB Slice SLICE ECE 545 – Introduction to VHDL Carry & Control Logic COUT YB Look-Up Table Carry & Control Logic Y G4 G3 G2 G1 S D Q O CK EC R F5IN BY SR XB Look-Up Table Carry & Control Logic X S F4 F3 F2 F1 D Q O The configurable logic block (CLB) contains two slices. Each slice contains two 4-input look-up tables (LUT), carry & control logic and two registers. There are two 3-state buffers associated with each CLB, that can be accessed by all the outputs of a CLB. Xilinx is the only major FPGA vendor that provides dedicated resources for on-chip 3-state bussing. This feature can increase the performance and lower the CLB utilization for wide multiplex functions. The Xilinx internal bus can also be extended off chip. CK EC R CIN CLK CE SLICE ECE 545 – Introduction to VHDL

Xilinx Multipurpose LUT The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 545 – Introduction to VHDL

Distributed RAM = or CLB LUT configurable as Distributed RAM RAM16X1S O D WE WCLK A0 A1 A2 A3 RAM32X1S A4 RAM16X2S O1 D0 D1 O0 = LUT or RAM16X1D SPO DPRA0 DPO DPRA1 DPRA2 DPRA3 CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual-Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width. The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT. The distributed ram is compact and fast which makes it ideal for small ram based functions. ECE 545 – Introduction to VHDL

Generic RAM – inferring Block RAM (2) ARCHITECTURE LUT_based_ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits-1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS(clk) IF (rising_edge(clk)) THEN IF(wr_ena=‘1’) THEN memory(addr) <= data_in; ELSE data_out <= memory(addr); END IF; END PROCESS; END LUT_based_RAM; ECE 545 – Introduction to VHDL

Report from Synthesis (2) Mapping to part: xc3s50pq208-5 Cell usage: GND 1 use RAMB16_S9 1 use VCC 1 use RAM/ROM usage summary Block Rams : 1 of 4 (25%) Mapping Summary: Total LUTs: 0 (0%) ECE 545 – Introduction to VHDL

Report from Implementation (2) Target Device : xc3s50 Target Package : pq208 Target Speed : -5 Design Summary -------------- Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 26 out of 124 20% Number of Block RAMs: 1 out of 4 25% Number of GCLKs: 1 out of 8 12% ECE 545 – Introduction to VHDL

Single-Port Block RAM ECE 545 – Introduction to VHDL

Generic ROM (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------- ENTITY rom IS GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 8); -- # of words in the memory PORT ( addr: IN INTEGER RANGE 0 TO words-1; data: OUT STD_LOGIC_VECTOR(bits – 1 DOWNTO 0) ); END rom; ECE 545 – Introduction to VHDL

Generic ROM (2) ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := ("0000_0000", "0000_0010", "0000_0100", "0000_1000", "0001_0000", "0010_0000", "0100_0000", "1000_0000"); BEGIN data <= memory(addr); END rom; ECE 545 – Introduction to VHDL

Generic ROM (3) – hexadecimal notation ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := (X"00", X"02", X"04", X"08", X"10", X"20", X"40", X"80"); BEGIN data <= memory(addr); END rom; ECE 545 – Introduction to VHDL

FPGA specific memories ECE 545 – Introduction to VHDL

Distributed RAM = or CLB LUT configurable as Distributed RAM RAM16X1S O D WE WCLK A0 A1 A2 A3 RAM32X1S A4 RAM16X2S O1 D0 D1 O0 = LUT or RAM16X1D SPO DPRA0 DPO DPRA1 DPRA2 DPRA3 CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual-Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width. The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT. The distributed ram is compact and fast which makes it ideal for small ram based functions. ECE 545 – Introduction to VHDL

RAM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity RAM_16X1_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC; DATA_OUT : out STD_LOGIC ); end RAM_16X1_DISTRIBUTED; ECE 545 – Introduction to VHDL

RAM 16x1 (2) architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is -- part used by the synthesis tool, Synplify Pro, only; ignored during simulation attribute INIT : string; attribute INIT of RAM16X1_S_1: label is "0000"; ------------------------------------------------------------------------ component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component; ECE 545 – Introduction to VHDL

RAM 16x1 (3) begin RAM_16X1_S_1: ram16x1s generic map (INIT => X”0000") port map (O => DATA_OUT, A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN, WCLK => CLK, WE => WE ); end RAM_16X1_DISTRIBUTED_STRUCTURAL; ECE 545 – Introduction to VHDL

RAM 16x8 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity RAM_16X8_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0) ); end RAM_16X8_DISTRIBUTED; ECE 545 – Introduction to VHDL

RAM 16x8 (2) architecture RAM_16X8_DISTRIBUTED_STRUCTURAL of RAM_16X8_DISTRIBUTED is attribute INIT : string; attribute INIT of RAM16X1_S_1: label is "0000"; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component; ECE 545 – Introduction to VHDL

RAM 16x8 (3) begin GENERATE_MEMORY: for I in 0 to 7 generate RAM_16X1_S_1: ram16x1s generic map (INIT => X"0000") port map (O => DATA_OUT(I), A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN(I), WCLK => CLK, WE => WE ); end generate; end RAM_16X8_DISTRIBUTED_STRUCTURAL; ECE 545 – Introduction to VHDL

ROM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity ROM_16X1_DISTRIBUTED is port( ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_OUT : out STD_LOGIC ); end ROM_16X1_DISTRIBUTED; ECE 545 – Introduction to VHDL

ROM 16x1 (2) architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of ROM_16X1_DISTRIBUTED is attribute INIT : string; attribute INIT of ROM16X1_S_1: label is "F0C1"; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component; signal Low : std_ulogic := ‘0’; ECE 545 – Introduction to VHDL

ROM 16x1 (3) begin ROM_16X1_S_1: ram16x1s generic map (INIT => X"F0C1") port map (O=>DATA_OUT, A0=>ADDR(0), A1=>ADDR(1), A2=>ADDR(2), A3=>ADDR(3), D=>Low, WCLK=>Low, WE=>Low ); end ROM_16X1_DISTRIBUTED_STRUCTURAL; ECE 545 – Introduction to VHDL

std_logic vs. std_ulogic TYPE std_ulogic IS (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’); SUBTYPE std_logic IS std_ulogic RANGE ‘X’ TO ‘-’; ECE 545 – Introduction to VHDL

Conversion std_logic_vector => integer (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity test is end test; architecture behavior of test is SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL u_addr: UNSIGNED(7 DOWNTO 0); SIGNAL i_addr : INTEGER; begin u_addr <= unsigned(stdl_addr); i_addr <= conv_integer(u_addr); end behavior; ECE 545 – Introduction to VHDL

Conversion std_logic_vector => integer (2) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity test is end test; architecture behavior of test is SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL i_addr : INTEGER; begin u_addr <= conv_integer(unsigned(stdl_addr)); end behavior; ECE 545 – Introduction to VHDL

Instruction ROM example (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY instruction_rom IS GENERIC ( w : INTEGER := 16; n : INTEGER := 8; m : INTEGER := 3); PORT ( Instr_addr : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0); Instr : out STD_LOGIC_VECTOR(w-1 DOWNTO 0) ); END instruction_rom; ECE 545 – Introduction to VHDL

Instruction ROM example (2) ARCHITECTURE ins_rom OF insstruction_rom IS SIGNAL temp: INTEGER RANGE 0 TO 7; TYPE vector_array IS ARRAY (0 to n-1) OF STD_LOGIC_VECTOR(w-1 DOWNTO 0); CONSTANT memory : vector_array := ( "0000_0000_0000_0000", "0000_0000_0000_0000", "1101_0100_0101_1001", "1101_0100_0101_1000", "0110_1000_1000_0111", "0100_1001_1001_1010", "1111_0110_0111_0101", "1111_0110_0111_0100", BEGIN temp <= conv_integer(unsigned(Instr_addr)); Instr <= memory(temp); END instruction_rom; ECE 545 – Introduction to VHDL

Generic dual-ported memory (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY memory_local IS PORT( wen : IN STD_LOGIC; clk : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0); addr1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); addr2 : IN STD_LOGIC_VECTOR (4 DOWNTO 0); data_out1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_out2: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END memory_local; ECE 545 – Introduction to VHDL

Generic dual-ported memory (2) ARCHITECTURE memory_local OF memory_local IS TYPE vector_array IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL memory : vector_array; SIGNAL temp1: INTEGER RANGE 0 TO 31; SIGNAL temp2: INTEGER RANGE 0 TO 31; BEGIN temp1 <= conv_integer(unsigned(addr1)); temp2 <= conv_integer(unsigned(addr2)); PROCESS(clk) IF (clk = '1' AND clk'event) THEN IF (wen = '1') THEN memory(temp2) <= data_in; END IF; END PROCESS; data_out1 <= memory(temp1); data_out2 <= memory(temp2); END memory_local; ECE 545 – Introduction to VHDL

Report from Implementation Target Device : xc3s50 Target Package : pq208 Target Speed : -5 Design Summary -------------- Logic Utilization: Number of 4 input LUTs: 66 out of 1,536 4% Logic Distribution: Number of occupied Slices: 97 out of 768 12% Number of Slices containing only related logic: 97 out of 97 100% Number of Slices containing unrelated logic: 0 out of 97 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 194 out of 1,536 12% Number used as logic: 66 Number used for Dual Port RAMs: 128 (Two LUTs used per Dual Port RAM) ECE 545 – Introduction to VHDL

Distributed RAM = or CLB LUT configurable as Distributed RAM RAM16X1S O D WE WCLK A0 A1 A2 A3 RAM32X1S A4 RAM16X2S O1 D0 D1 O0 = LUT or RAM16X1D SPO DPRA0 DPO DPRA1 DPRA2 DPRA3 CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual-Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width. The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT. The distributed ram is compact and fast which makes it ideal for small ram based functions. ECE 545 – Introduction to VHDL

Constants ECE 545 – Introduction to VHDL

Constants Syntax: CONSTANT name : type := value; Examples: CONSTANT high : STD_LOGIC := ‘1’; CONSTANT datamemory : memory := ((X"00", X"02"); ECE 545 – Introduction to VHDL

Constants - features Constants can be declared in a PACKAGE, ENTITY, ARCHITECTURE When declared in a PACKAGE, the constant is truly global, for the package can be used in several entities. When declared in an ARCHITECTURE, the constant is local, i.e., it is visible only within this architecture. When declared in an ENTITY, the constant can be used in all architectures associated with this entity. ECE 545 – Introduction to VHDL

Specifying time in VHDL ECE 545 – Introduction to VHDL

Physical data types Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types. TIME is the only predefined physical data type. Value of the physical data type is called a physical literal. ECE 545 – Introduction to VHDL

Time values (physical literals) - Examples 7 ns 1 min min 10.65 us 10.65 fs Numeric value Space Unit of time (dimension) ECE 545 – Introduction to VHDL

TIME values Numeric value can be an integer or a floating point number. Numeric value is optional. If not given, 1 is implied. Numeric value and dimension MUST be separated by a space. ECE 545 – Introduction to VHDL

Units of time Unit Definition Base Unit fs femtoseconds (10-15 seconds) Derived Units ps picoseconds (10-12 seconds) ns nanoseconds (10-9 seconds) us microseconds (10-6 seconds) ms miliseconds (10-3 seconds) sec seconds min minutes (60 seconds) hr hours (3600 seconds) ECE 545 – Introduction to VHDL

Values of the type TIME Value of a physical literal is defined in terms of integral multiples of the base unit, e.g. 10.65 us = 10,650,000,000 fs 10.65 fs = 10 fs Smallest available resolution in VHDL is 1 fs. Smallest available resolution in simulation can be set using a simulator command or parameter. ECE 545 – Introduction to VHDL

Arithmetic operations on values of the type TIME Examples: 7 ns + 10 ns = 17 ns 1.2 ns – 12.6 ps = 1187400 fs 5 ns * 4.3 = 21.5 ns 20 ns / 5ns = 4 ECE 545 – Introduction to VHDL

Records ECE 545 – Introduction to VHDL

Records – Examples (1) type opcodes is (add, sub, and, or); type reg_number is range 0 to 8; type instruction is record opcode: opcodes; source_reg1: reg_number; source_reg2: reg_number; dest_reg: reg_number; displacement: integer; end record instruction ECE 545 – Introduction to VHDL

Records – Examples (2) type word is record instr: instruction; data: bit_vector(31 downto 0); end record instruction; constant add_instr_1_3: instruction:= (opcode => add, source_reg1 | dest_reg => 1, source_reg2 => 3, displacement => 0); ECE 545 – Introduction to VHDL

Asserts & Reports ECE 545 – Introduction to VHDL

Assert Assert is a non-synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation. Depending on the severity of the problem, The simulator is instructed to continue simulation or halt. ECE 545 – Introduction to VHDL

Assert - syntax ASSERT condition [REPORT "message" [SEVERITY severity_level ]; The message is written when the condition is FALSE. Severity_level can be: Note, Warning, Error (default), or Failure. ECE 545 – Introduction to VHDL

Assert - Examples assert initial_value <= max_value report "initial value too large" severity error; assert packet_length /= 0 report "empty network packet received" severity warning; assert false report "Initialization complete" severity note; ECE 545 – Introduction to VHDL

Report - syntax REPORT "message" [SEVERITY severity_level ]; The message is always written. Severity_level can be: Note (default), Warning, Error, or Failure. ECE 545 – Introduction to VHDL

Report - Examples report "Initialization complete"; report "Current time = " & time'image(now); report "Incorrect branch" severity error; ECE 545 – Introduction to VHDL

Variables ECE 545 – Introduction to VHDL

Variable – Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Numbits IS PORT ( X : IN STD_LOGIC_VECTOR(1 TO 3) ; Count : OUT INTEGER RANGE 0 TO 3) ; END Numbits ; ECE 545 – Introduction to VHDL

Variable – Example (2) ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS(X) – count the number of bits in X equal to 1 VARIABLE Tmp: INTEGER; Tmp := 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp := Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ; ECE 545 – Introduction to VHDL

Variables - features Can only be declared within processes and subprograms (functions & procedures) Initial value can be explicitly specified in the declaration When assigned take an assigned value immediately Variable assignments represent the desired behavior, not the structure of the circuit Should be avoided, or at least used with caution in a synthesizable code ECE 545 – Introduction to VHDL

Advanced Testbenches ECE 545 – Introduction to VHDL

Using Arrays of Test Vectors In Testbenches ECE 545 – Introduction to VHDL

Testbench (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sevenSegmentTB is END sevenSegmentTB; ARCHITECTURE testbench OF sevenSegmentTB IS COMPONENTsevenSegment PORT ( bcdInputs : IN STD_LOGIC_VECTOR (3 DOWNTO 0); seven_seg_outputs : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); ); end COMPONENT; CONSTANT PropDelay: time := 40 ns; CONSTANT SimLoopDelay: time := 10 ns; ECE 545 – Introduction to VHDL

Testbench (2) TYPE vector IS RECORD bcdStimulus: STD_LOGIC_VECTOR(3 downto 0); sevSegOut: STD_LOGIC_VECTOR(6 downto 0); END RECORD; CONSTANT NumVectors: INTEGER:= 10; TYPE vectorArray is ARRAY (0 TO NumVectors - 1) OF vector; CONSTANT vectorTable: vectorArray := ( (bcdStimulus => "0000", sevSegOut => "0000001"), (bcdStimulus => "0001", sevSegOut => "1001111"), (bcdStimulus => "0010", sevSegOut => "0010010"), (bcdStimulus => "0011", sevSegOut => "0000110"), (bcdStimulus => "0100", sevSegOut => "1001100"), (bcdStimulus => "0101", sevSegOut => "0100100"), (bcdStimulus => "0110", sevSegOut => "0100000"), (bcdStimulus => "0111", sevSegOut => "0001111"), (bcdStimulus => "1000", sevSegOut => "0000000"), (bcdStimulus => "1001", sevSegOut => "0000100") ); ECE 545 – Introduction to VHDL

Testbench (3) SIGNAL StimInputs: STD_LOGIC_VECTOR(3 downto 0); SIGNAL CaptureOutputs: STD_LOGIC_VECTOR(6 downto 0); BEGIN u1: sevenSegment PORT MAP ( bcdInputs => StimInputs, seven_seg_outputs => CaptureOutputs); ECE 545 – Introduction to VHDL

Testbench (4) LoopStim: PROCESS BEGIN FOR i in 0 TO NumVectors-1 LOOP StimInputs <= vectorTable(i).bcdStimulus; WAIT FOR PropDelay; ASSERT CaptureOutputs == vectorTable(i).sevSegOut REPORT “Incorrect Output” SEVERITY error; WAIT FOR SimLoopDelay; END LOOP; ECE 545 – Introduction to VHDL

Testbench (5) WAIT; END PROCESS; END testbench; ECE 545 – Introduction to VHDL

File I/O ECE 545 – Introduction to VHDL

Design Under Test (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY loadCnt IS PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0); load: IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END loadCnt; ECE 545 – Introduction to VHDL

Design Under Test (2) ARCHITECTURE rtl OF loadCnt IS SIGNAL cnt: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN counter: PROCESS (clk, rst) IF (rst = '1') THEN cnt <= (OTHERS => '0'); ELSIF (clk'event AND clk = '1') THEN IF (load = '1') THEN cnt <= data; ELSE cnt <= cnt + 1; END IF; END PROCESS; q <= cnt; END rtl; ECE 545 – Introduction to VHDL

Test vector file (1) #Format is Rst, Load, Data, Q #load the counter to all 1s 0 1 11111111 11111111 #reset the counter 1 0 10101010 00000000 #now perform load/increment for each bit 0 1 11111110 11111110 0 0 11111110 11111111 # 0 1 11111101 11111101 0 0 11111101 11111110 0 1 11111011 11111011 0 0 11111011 11111100 0 1 11110111 11110111 0 0 11110111 11111000 ECE 545 – Introduction to VHDL

Test vector file (2) # 0 1 11101111 11101111 0 0 11101111 11110000 0 1 11011111 11011111 0 0 11011111 11100000 0 1 10111111 10111111 0 0 10111111 11000000 0 1 01111111 01111111 0 0 01111111 10000000 #check roll-over case 0 1 11111111 11111111 0 0 11111111 00000000 # End vectors ECE 545 – Introduction to VHDL

Testbench (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_textio.all; LIBRARY std; USE std.textio.all; ENTITY loadCntTB IS END loadCntTB; ECE 545 – Introduction to VHDL

Testbench (2) ARCHITECTURE testbench OF loadCntTB IS COMPONENT loadCnt PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0); load: IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; q: OUT STD_LOGC_VECTOR (7 DOWNTO 0) ); END COMPONENT; ECE 545 – Introduction to VHDL

Testbench (3) FILE vectorFile: TEXT OPEN READ_MODE is "vectorfile.txt"; TYPE vectorType IS RECORD data: STD_LOGIC_VECTOR(7 DOWNTO 0); load: STD_LOGIC; rst: STD_LOGIC; q: STD_LOGIC_VECTOR(7 DOWNTO 0); END RECORD; SIGNAL testVector: vectorType; SIGNAL Qout: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL TestClk: STD_LOGIC := '0'; CONSTANT ClkPeriod: TIME := 100 ns; ECE 545 – Introduction to VHDL

Testbench (4) BEGIN -- Free running test clock TestClk <= NOT TestClk AFTER ClkPeriod/2; -- Instance of design being tested u1: loadCnt PORT MAP (Data => testVector.Data, load => testVector.Load, clk => TestClk, rst => testVector.Rst, q => Qout ); ECE 545 – Introduction to VHDL

Testbench (5) -- File reading and stimulus application readVec: PROCESS VARIABLE VectorLine: LINE; VARIABLE VectorValid: BOOLEAN; VARIABLE vRst: STD_LOGIC; VARIABLE vLoad: STD_LOGIC; VARIABLE vData: STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE vQ: STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE space: CHARACTER; ECE 545 – Introduction to VHDL

Testbench (5) BEGIN WHILE NOT ENDFILE (vectorFile) LOOP readline(vectorFile, VectorLine); read(VectorLine, vRst, good => VectorValid); NEXT WHEN NOT VectorValid; read(VectorLine, space); read(VectorLine, vLoad); read(VectorLine, vData); read(VectorLine, vQ); WAIT FOR ClkPeriod/4; ECE 545 – Introduction to VHDL

Testbench (6) testVector.Rst <= vRst; testVector.Load <= vLoad; testVector.Data <= vData; testVector.Q <= vQ; WAIT FOR (ClkPeriod/4) * 3; END LOOP; ASSERT FALSE REPORT "Simulation complete" SEVERITY NOTE; WAIT; END PROCESS; ECE 545 – Introduction to VHDL

Testbench (7) -- Process to verify outputs verify: PROCESS (TestClk) variable ErrorMsg: LINE; BEGIN IF (TestClk'event AND TestClk = '0') THEN IF Qout /= testVector.Q THEN write(ErrorMsg, STRING'("Vector failed ")); write(ErrorMsg, now); writeline(output, ErrorMsg); END IF; END PROCESS; END testbench; ECE 545 – Introduction to VHDL

Hex format In order to read/write data in the hexadecimal notation, replace read with hread, and write with hwrite ECE 545 – Introduction to VHDL