ANALYSIS OF SEQUENTIAL CIRCUIT LOGIC DIAGRAM

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ANALYSIS OF SEQUENTIAL CIRCUIT LOGIC DIAGRAM J.SHEIK SHABJAN M.Sc., M.Phil., SET ASSISTANT PROFESSOR DEPARTMENT OF ELECTRONICS St. JOSEPH’S COLLEGE (Autonomous), TRICHY

SYNCHRONOUS SEQUENTIAL CIRCUIT WITH A T FLIP FLOP Let explore the behavior of the circuit in fig by developing a timing diagram, state table and state diagram X = 01101000

T FLIP FLOP

The logic equations for the example are The input sequence is Assume starting state is y = 0

Timing diagram Notice that all the input transitions are not synchronized with the clock pulse.

State diagram and state table

SYNCHRONOUS SEQUENTIAL CIRCUIT WITH JK FLIP FLOPS X = 0011110

JK FLIP FLOP

Z = 0000010 The logic equations for the example are The input sequence is Assume starting state is The output sequence is Z = 0000010 9

Timing diagram

State table

SYNCHRONOUS SEQUENTIAL CIRCUIT SYNTHESIS

TYPES OF SEQUENTIAL CIRCUITS Completely specified circuit Incompletely specified circuit

Synthesis Procedure Let us find a clocked D flip flop realization for the sequential circuit defined in the state table