The SDRAM Controller EECS150 Fall2008 - Lab Lecture #8 Chen Sun Adopted from slides designed by Greg Gibeling and Chen Sun 10/17/2008 EECS150 Lab Lecture #7 EECS150 Lab Lecture #8 1

Today Checkpoint 2 and Checkpoint 3 Administrative Info SDRAM and Multiport Arbitration Theory of SDRAM SDRAM Controller Design Tips Reading Synthesis reports 10/17/2008 EECS150 Lab Lecture #7 EECS150 Lab Lecture #8 2

Checkpoints 2 & 3: Motivation Learn to configure external SDRAM Design a memory controller Write and read from external SDRAM To use FIFOs as buffers Learn how to read very long datasheets SDRAM (Checkpoint #2) Multiport Arbitration (checkpoint #3) 10/17/2008 EECS150 Lab Lecture #8

Checkpoint 2: Goals Initialize and configure SDRAM Abstract away complex DRAM interface into simple Request/Valid signals Practice writing good, effective testbenches 10/17/2008 EECS150 Lab Lecture #8

Checkpoint 2: Tasks We give you… Checkoff MT48LC16M16A2.v SDRAM Modelsim simulation model Checkoff Simulate in Modelsim with MT48LC16M16A2.v We will also provide checkpoint0bb, for those who wish to do a hardware test (optional) Highly recommended to get it working in hardware at this point 10/17/2008 EECS150 Lab Lecture #8

Checkpoint 3: Overview Put what you simulated on board Design an Arbiter to handle simultaneous SDRAM requests We give you… 32-bit data generator (checkpoint0bb) Checkoff Camera  SDRAM  Video Encoder 10/17/2008 EECS150 Lab Lecture #8

Administrative Info Be wary of your deadlines! Checkpoint 1: Check off by Friday, 10/24 2:10 pm Checkpoint 2: Design Review week of 10/20. Check off by Friday, 10/31 2:10pm Checkpoint 3: Lab lecture next week 10/24. Note that you will be designing your next checkpoint while implementing the current checkpoint! 10/17/2008 EECS150 Lab Lecture #8

SDRAM Introduction Typical consumer SDRAM: SDRAM found on the Calinx2: KVR133X64C3/256 256MB 32M x 64-Bit PC133 CL3 168-Pin DIMM Module (aka Kingston “ValueRAM”) SDRAM found on the Calinx2: MT48LC16M16A2 - 7E 64MB x 16-Bit PC133 CL2 (2 of these per Calinx2) http://www.micron.com/products/partdetail?part=MT48LC16M16A2TG-75 http://www.newegg.com/Product/Product.aspx?Item=N82E16820134157 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (1) SDRAM: Synchronous Dynamic RAM “Static” RAM: stored values have a constant connection to either 1 or 0 I.e. the output of a register always connected to a 1 or 0. It never “floats” “Dynamic” RAM: charge is stored in a capacitor. (no charge = 0, charge = 1) A connection is made to either 1 or 0 only when a write is performed. 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (2) Typical DRAM cell: 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (3) Advantages of SDRAM Each cell takes very little resources to implement (fit a lot in a small area) Cheap to make BIG capacity SDRAM adds a Clock signal to DRAM, to synchronize outputs to that Clock 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (4) Disadvantages of SDRAM Too big: Lots of address bits Dynamic: Capacitors leak! Dynamic: Capacitors are small and do not store much charge Reads become unreliable Dynamic: Reads are destructive to the data High latency accesses 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (5) SDRAM is big. Need lots of bits for address Lots of leads coming out from SDRAM chips Solution: Time-divide the address Send row addresses first Wait a bit Then send column addresses 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (6) Problem: Capacitors leak! The value stored in the capacitor slowly leaks away after some time period Solution: Refresh stored values SDRAM must periodically go and read out values it hasn’t used in a while, then write them back in SDRAM needs to find free time to do this 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (7) Problem: Capacitors small Solution: Precharge Not enough charge stored to bring the bit line all the way to logic 1 or 0 on a read Solution: Precharge Charge the bit line to halfway, then hope the small amount of charge stored in capacitor just enough to tip it to a 1 or 0 Need good sense amplifiers to detect the small change 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (8) Problem: Reads are destructive Capacitor uses stored charge on a read Value stored in capacitor will change Solution: Write back after reading After we do the read, we must write what we just read back into the SDRAM 10/17/2008 EECS150 Lab Lecture #8

Theory of SDRAM (9) Problem: High latency accesses Takes a while for SDRAM to go to the row and columns and write or read data Solution: FIFOs, latency-insensitive and interface-driven design! More on this in Checkpoint 3 These potential problems greatly influenced the SDRAM interface 10/17/2008 EECS150 Lab Lecture #8

SDRAM Controller (1) Goal: Abstract away the complex SDRAM interface Provide a simple Request/DataValid interface all other modules can use Good news: the SDRAM hardware given will automatically do a lot of things that resolve the problems mentioned previously 10/17/2008 EECS150 Lab Lecture #8

SDRAM Controller (2) Bad news: you have to figure out how to turn on some of those features We will help you by pointing out specific pages in the spec that will be helpful Keep in mind that we will be running this at only 27 MHz! The SDRAM was designed for 133 MHz Many timing restrictions do not apply at 27 MHz 10/17/2008 EECS150 Lab Lecture #8

SDRAM Controller (3) SDRAM is a large FSM SDRAM Controller’s Job Send it a command Get a response SDRAM Controller’s Job Initialize SDRAM Send the right command signals Ensure command sequences are timed correctly Another large FSM 10/17/2008 EECS150 Lab Lecture #8

SDRAM Controller (4) Become familiar with timing diagrams Off-by-one-cycle errors could cause your SDRAM controller to not work MT48LC16M16A2 Datasheet - your primary source of information Official Checkpoint 2 spec - gives the specifics about what we want Also narrows down the important pages to read from the datasheet 10/17/2008 EECS150 Lab Lecture #8

Read Operation 10/17/2008 EECS150 Lab Lecture #8

Write Operation 10/17/2008 EECS150 Lab Lecture #8

Write Timing 10/17/2008 EECS150 Lab Lecture #8

Design Tips (1) Synthesis warnings When you find a bug, the first thing to do is to check synthesis warnings Synplify Pro has a much stricter syntax check than Modelsim It will let you know if it finds anything weird with your code Synplify will not pass with Errors But IT WILL PASS with warnings! 10/17/2008 EECS150 Lab Lecture #8

Design Tips (2) Sample synthesis report: Message Types: @N: CG364 :"C:\Test.v":21:7:21:10|Synthesizing module Test @W: CG133 :"C:\Test.v":26:15:26:19|No assignment to IfOut @W: CL153 :"C:\Test.v":26:15:26:19|*Unassigned bits of IfOut have been referenced and are being tied to 0 - simulation mismatch possible @W: CL159 :"C:\Test.v":24:14:24:18|Input Reset is unused Message Types: @N: Note - Synplify pro is just telling you about what it just did. Nothing to worry about for these messages @W: Warning - Synplify pro found something weird with your code, but will continue. Make sure you know what you are doing @E: Error - Synplify pro cannot continue synthesis due to a syntax error or some extremely weird thing you tried to do 10/17/2008 EECS150 Lab Lecture #8

Design Tips (3) Sample synthesis report: @N: CG364 :"C:\Test.v":21:7:21:10|Synthesizing module Test @W: CG133 :"C:\Test.v":26:15:26:19|No assignment to IfOut @W: CL153 :"C:\Test.v":26:15:26:19|*Unassigned bits of IfOut have been referenced and are being tied to 0 - simulation mismatch possible @W: CL159 :"C:\Test.v":24:14:24:18|Input Reset is unused Which module generated the message? This tells you which module the message came from. Generally, if it came from a module that was given to you (i.e. FPGA_TOP2+.v), you do not need to worry about any warnings it gives out since it was most likely not caused by you 10/17/2008 EECS150 Lab Lecture #8

Design Tips (4) Sample synthesis report: @N: CG364 :"C:\Test.v":21:7:21:10|Synthesizing module Test @W: CG133 :"C:\Test.v":26:15:26:19|No assignment to IfOut @W: CL153 :"C:\Test.v":26:15:26:19|*Unassigned bits of IfOut have been referenced and are being tied to 0 - simulation mismatch possible @W: CL159 :"C:\Test.v":24:14:24:18|Input Reset is unused What line in the module generated the message? Just tells you what line in the file triggered the message that was sent EXTREMELY useful for catching syntax errors 10/17/2008 EECS150 Lab Lecture #8

Design Tips (5) Sample synthesis report: Description of the message @N: CG364 :"C:\Test.v":21:7:21:10|Synthesizing module Test @W: CG133 :"C:\Test.v":26:15:26:19|No assignment to IfOut @W: CL153 :"C:\Test.v":26:15:26:19|*Unassigned bits of IfOut have been referenced and are being tied to 0 - simulation mismatch possible @W: CL159 :"C:\Test.v":24:14:24:18|Input Reset is unused Description of the message What was the message Warnings and errors will tell you what exactly caused it to send the warning/error 10/17/2008 EECS150 Lab Lecture #8

Design Tips (6) Extremely common synthesis warnings that can lead to major problems: Latch generated ... Port mismatch ... Caused by, for example, connecting a 32-bit wire to an 8-bit port Pruning instance ... Synplify Pro optimizes your design by getting rid of stuff it thinks you do not use. Make sure it is not pruning something you believe you are using! Input … unused … Make sure you really intend not to use that input No assignment to variable … Did you really mean to never do anything with that variable? Unassigned bits of … have been referenced and being tied to zero You did not connect that output to anything 10/17/2008 EECS150 Lab Lecture #8

Design Tips (7) The list of synthesis warnings goes on and on… View RTL schematic Another great place to look at what Synplify Pro turned your circuit into Great for finding missing port connections and wires! 10/17/2008 EECS150 Lab Lecture #8