Is Statistical Timing Statistically Significant?

Slides:



Advertisements
Similar presentations
ITRS December 2003, Hsin-Chu Taiwan How Much Variability Can Designers Tolerate? Andrew B. Kahng ITRS Design ITWG December 1, 2003.
Advertisements

Explicit vs Implicit. Explicit: Explicit: A function defined in terms of one variable. y= 3x + 2 is defined in terms of x only. Implicit: Implicit: A.
Slide 1 Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed- Signal Circuits by Reusing Early-Stage Data Fa Wang*, Wangyang Zhang*,
4/22/ Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731.
Keeping Hot Chips Cool Ruchir Puri, Leon Stok, Subhrajit Bhattacharya IBM T.J. Watson Research Center Yorktown Heights, NY Circuits R-US.
On the Need for Statistical Timing Analysis Farid N. Najm University of Toronto
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 23: April 10, 2013 Statistical Static Timing Analysis.
Copyright © 2008 by the McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill/Irwin Managerial Economics, 9e Managerial Economics Thomas Maurice.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 23: April 22, 2009 Statistical Static Timing Analysis.
Puneet Sharma and Puneet Gupta Prof. Andrew B. Kahng Prof. Dennis Sylvester System-Level Living Roadmap Annual Review, Sept Basic Ideas Gate-length.
University of Michigan Advanced Computer Architecture Lab. March 21, Key PED Challenges David Blaauw University of Michigan
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 14: March 19, 2008 Statistical Static Timing Analysis.
Statistical timing and synthesis Chandu paper. Canonical form Compute max(A,B) = C in canonical form (assuming  X i independent)
Correlation MARE 250 Dr. Jason Turner.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 22: April 11, 2011 Statistical Static Timing Analysis.
Focus group: Statistical synthesis. Top reasons to go for statistical Often cited - worst case is way off - exact SI and IR drop analysis is too complex.
© 2005 Altera Corporation © 2006 Altera Corporation Placement and Timing for FPGAs Considering Variations Yan Lin 1, Mike Hutton 2 and Lei He 1 1 EE Department,
Jan. 2007VLSI Design '071 Statistical Leakage and Timing Optimization for Submicron Process Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn.
Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control Puneet Gupta 1 Andrew B. Kahng 1 Puneet Sharma 1 Dennis Sylvester 2 1 ECE Department,
UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.
© Chandu Visweswariah, 2004Statistical Analysis and Design: From Picoseconds to Probabilities1 of 80 Statistical Analysis and Design: From Picoseconds.
Cloud Data Center/Storage Power Efficiency Solutions Junyao Zhang 1.
Energy Efficient Routing and Self-Configuring Networks Stephen B. Wicker Bart Selman Terrence L. Fine Carla Gomes Bhaskar KrishnamachariDepartment of CS.
CRESCENDO Full virtuality in design and product development within the extended enterprise Naples, 28 Nov
Power Reduction for FPGA using Multiple Vdd/Vth
UC San Diego / VLSI CAD Laboratory Toward Quantifying the IC Design Value of Interconnect Technology Improvement Tuck-Boon Chan, Andrew B. Kahng, Jiajia.
Copyright © 2005 by the McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill/Irwin Managerial Economics Thomas Maurice eighth edition Chapter 4.
Chapter 8 CPU and Memory: Design, Implementation, and Enhancement The Architecture of Computer Hardware and Systems Software: An Information Technology.
© Chandu Visweswariah, 2004New Challenges in IC Design1 New Challenges in IC Design … with a focus on variability … SBCCI 2004 Panel Discussion Chandu.
Inferential Statistics A Closer Look. Analyze Phase2 Nature of Inference in·fer·ence (n.) “The act or process of deriving logical conclusions from premises.
MAT 1228 Series and Differential Equations Section 3.7 Nonlinear Equations
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.
Is Statistical Timing Statistically Significant? DAC 2004, Panel Discussion, Session 41 Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown.
Implicit Differentiation. Implicitly vs. Explicitly Defined Functions y is given explicitly as a function of x (y is solved in terms of x) y is given.
1 Tau 2002 Explicit Computation of Performance as a Function of Process Parameters Lou Scheffer.
1 Carnegie Mellon University Center for Silicon System Implementation An Architectural Exploration of Via Patterned Gate Arrays Chetan Patel, Anthony Cozzie,
Patricia Gonzalez Divya Akella VLSI Class Project.
Thomas J. Watson Research Center © 2006 IBM Corporation Statistical Timing in a Practical 65 nm Robust Design Flow Chandu Visweswariah.
Unified Adaptivity Optimization of Clock and Logic Signals Shiyan Hu and Jiang Hu Dept of Electrical and Computer Engineering Texas A&M University.
University of Michigan Advanced Computer Architecture Lab. 2 CAD Tools for Variation Tolerance David Blaauw and Kaviraj Chopra University of Michigan.
Gopakumar.G Hardware Design Group
Advanced Architectures
Rouwaida Kanj, *Rajiv Joshi, and Sani Nassif
Basic Estimation Techniques
Basic Practice of Statistics - 5th Edition
Basic Project Scheduling
Design Methodology for Semi Custom Processor Cores
STA 282 Introduction to Statistics
Buffer Insertion with Adaptive Blockage Avoidance
Challenges in Nanoelectronics: Process Variability
Basic Estimation Techniques
Out-of-Order Commit Processor
Timing Optimization Andreas Kuehlmann
ITRS Design.
Testing for Faults, Looking for Defects
Investigating associations between categorical variables
Circuit Design Techniques for Low Power DSPs
Yiyu Shi*, Wei Yao*, Jinjun Xiong+ and Lei He*
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
Descriptive and Inferential
Post-Silicon Calibration for Large-Volume Products
Statistical Data Analysis
Statistical Analysis and Design: From Picoseconds to Probabilities
New Challenges in IC Design … with a focus on variability …
Measuring the Gap between FPGAs and ASICs
Solving Polynomials by Factoring
Unit 4. Day 13..
Parametric Yield Estimation Considering Leakage Variability Rajeev Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester Present by Fengbo Ren Apr. 30.
Chapter 9 Estimation: Additional Topics
ECE 576 POWER SYSTEM DYNAMICS AND STABILITY
Presentation transcript:

Is Statistical Timing Statistically Significant? DAC 2004, Panel Discussion, Session 41 Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY

The march of technology Performance Is this worth a huge investment? Technology generation

Corner-based vs. statistical n = # independent sources of variation (say 9)  = total variability in critical path delay (say 5%) Fractional increase in frequency with a 3 sign-off instead of 3n sign-off Assumes sources of variation are roughly equally significant

Corner-based vs. statistical

Simultaneous power/timing sign-off Probability Good chips Too slow Too leaky Vt

Where will the models come from? Clearly, the IDMs have an advantage Table-based delay modeling formats are not as conducive to statistical timing as equation-based formats

Can statistical timers handle the size? 2.1M gate design timed in 69 minutes with 10.9 GB memory 1.1M gate design timed in 110 minutes (dominated by load time) with 4.3 GB memory

BEOL early-mode variability on ASIC part Exhaustive corner analysis: -225 ps Pessimism reduction -3 slack: -162 ps

How will it be phased in? Phase 1 true 3 timing sign-off with statistical timing Phase 2 use statistical timing to guide the physical synthesis and routing optimization (implicit robustness credit) Phase 3 further reduce performance  by actively targeting robustness (explicit robustness credit) Phase 4 with the mainstream availability of at-speed test, enable yield/performance tradeoffs

Propositions/predictions Variability is proportionately increasing; therefore, a new paradigm is required Correlated vs. independent variability matters Statistical timing tools are rising to the challenge Robustness is an important metric Statistical treatment of variability will pervade all aspects of chip design and manufacturing ASICs and processors will both benefit (in that order)

Statistical prediction (ASICs) With a probability of ____%, statistical design analysis will have been used at the _______ technology node by the year ______, to solve the problem of ___________________________. The technical foundation of this statistical design analysis will be __________________________ ______________________. 99 90 nm 2006 performance pessimism (in part) techniques like those of paper 21.1