Improved Random Pattern Delay Fault Coverage Using Inversion Test Points Soham Roy, Brandon Steine, Spencer Millican, Vishwani Agrawal Dept. of Electrical.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Design Methodologies Design for Test.

Advertisements

Weighted Random and Transition Density Patterns for Scan-BIST Farhana Rashid* Vishwani D. Agrawal Auburn University ECE Department, Auburn, Alabama

An Algorithm for Diagnostic Fault Simulation Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA 13/29/2010IEEE LATW 10.

1 Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan Vishwani D. Agrawal Department of Electrical and Computer.

1 A Random Access Scan Architecture to Reduce Hardware Overhead Anand S. Mudlapur Vishwani D. Agrawal Adit D. Singh Department of Electrical and Computer.

1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL Hillary Grimes & Vishwani D. Agrawal.

Robust Low Power VLSI ECE 7502 S2015 Delay Test ECE 7502 Class Discussion He Qi March 19, 2015.

Designing Variation-Tolerance in Mixed-Signal Components of a System-on-Chip Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn.

Scalable Test Pattern Generator Design Method for BIST Petr Fišer, Hana Kubátová Czech Technical University in Prague Faculty of Electrical Engineering.

Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849

Dynamic SCAN Clock control In BIST Circuits

Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

Diagnostic Test Generation and Fault Simulation Algorithms for Transition Faults Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama

Dual Voltage Design for Minimum Energy Using Gate Slack Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University Auburn, AL 36849, USA IEEE ICIT-SSST.

Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA.

Design of Variable Input Delay Gates for Low Dynamic Power Circuits

5/1/2006VTS'061 Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring Vishwani D. Agrawal Auburn University, Dept. of ECE, Auburn,

Dec. 19, 2005ATS05: Agrawal and Doshi1 Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849,

Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Vishwani D. Agrawal Alok S. Doshi.

Practically Realizing Random Access Scan By Anand Mudlapur ECE Dept. Auburn University.

Priyadharshini Shanmugasundaram Vishwani D. Agrawal DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING.

5/7/2007VTS'071 Delay Test Quality Evaluation Using Bounded Gate Delays Soumitra Bose Intel Corporation, Design Technology, Folsom, CA Vishwani D.

1 Oct 24-26, 2006 ITC'06 Fault Coverage Estimation for Non-Random Functional Input Sequences Soumitra Bose Intel Corporation, Design Technology, Folsom,

10/25/2007 ITC-07 Paper Delay Fault Simulation with Bounded Gate Delay Model Soumitra Bose Design Technology, Intel Corp. Folsom, CA Hillary.

9/21/04ELEC / Class Projects 1 ELEC / /Fall 2004 Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and.

Independence Fault Collapsing

Jan 6-10th, 2007VLSI Design A Reduced Complexity Algorithm for Minimizing N-Detect Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.

Aug. 13, 2005Mudlapur et al.: VDAT'051 A Novel Random Access Scan Flip-Flop Design Anand S. Mudlapur Vishwani D. Agrawal (Speaker) Adit D. Singh Department.

Jan. 6, 2006VLSI Design '061 On the Size and Generation of Minimal N-Detection Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.

March 6, th Southeastern Symposium on System Theory1 Transition Delay Fault Testing of Microprocessors by Spectral Method Nitin Yogi and Vishwani.

1 Enhancing Random Access Scan for Soft Error Tolerance Fan Wang* Vishwani D. Agrawal Department of Electrical and Computer Engineering, Auburn University,

Finding Optimum Clock Frequencies for Aperiodic Test Master’s Thesis Defense Sindhu Gunasekar Dept. of ECE, Auburn University Advisory Committee: Dr. Vishwani.

Testimise projekteerimine: Labor 2 BIST Optimization

Master’s Thesis Defense Xiaolu Shi Dept. of ECE, Auburn University

Muralidharan Venkatasubramanian Vishwani D. Agrawal

PRAVEEN VENKATARAMANI VISHWANI D. AGRAWAL Auburn University, Dept. of ECE Auburn, AL 36849, USA 26 th International.

1 Compacting Test Vector Sets via Strategic Use of Implications Kundan Nepal Electrical Engineering Bucknell University Lewisburg, PA Nuno Alves, Jennifer.

VTS 2012: Zhao-Agrawal1 Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal Department of Electrical and Computer.

Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Engg. Auburn, AL 36849, U.S.A. Nitin Yogi NVIDIA Corporation, Santa Clara, CA th.

X-Alignment Techniques for Improving the Observability of Response Compactors Ozgur Sinanoglu Sobeeh Almukhaizim† Math & Computer Science Department Computer.

Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors Amir Yazdanbakhsh, David Palframan, Azadeh Davoodi, Mikko Lipasti, Nam Sung.

A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume Wei-Cheng Lien 1, Kuen-Jong Lee 1 and Tong-Yu.

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects Fei Wang 1,2, Yu Hu 1, Huawei Li 1, Xiaowei Li 1, Jing Ye 1,2 1 Key Laboratory.

November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan1 Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi.

ELEC 7950 – VLSI Design and Test Seminar

POWER OPTIMIZATION IN RANDOM PATTERN GENERATOR By D.Girish Kumar 108W1D8007.

July 10, th VLSI Design and Test Symposium1 BIST / Test-Decompressor Design using Combinational Test Spectrum Nitin Yogi Vishwani D. Agrawal Auburn.

` Printing: This poster is 48” wide by 36” high. It’s designed to be printed on a large-format printer. Customizing the Content: The placeholders in this.

Fault-Tolerant Resynthesis for Dual-Output LUTs Roy Lee 1, Yu Hu 1, Rupak Majumdar 2, Lei He 1 and Minming Li 3 1 Electrical Engineering Dept., UCLA 2.

ELEC 7770 Advanced VLSI Design Spring 2016 Introduction

Hardware Testing and Designing for Testability

COUPING WITH THE INTERCONNECT

VLSI Testing Lecture 14: Built-In Self-Test

VLSI Testing Lecture 6: Fault Simulation

VLSI Testing Lecture 7: Combinational ATPG

Muralidharan Venkatasubramanian Ph. D Proposal Exam Chair

Pattern Compression for Multiple Fault Models

ELEC 7770 Advanced VLSI Design Spring 2012 Introduction

ELEC 7770 Advanced VLSI Design Spring 2010 Introduction

Testing for Faults, Looking for Defects

ELEC-7250 VLSI Testing Scan Design Implementation on ISCAS ’89 Benchmark Circuits – s1423 and s1512 Completed by: Jonathan Harris.

VLSI Testing Lecture 8: Sequential ATPG

Fault Models, Fault Simulation and Test Generation

A Primal-Dual Solution to Minimal Test Generation Problem

VLSI Testing Lecture 7: Combinational ATPG

Testing in the Fourth Dimension

VLSI Testing Lecture 9: Delay Test

VLSI Testing Lecture 7: Delay Test

Lecture 26 Logic BIST Architectures

A Random Access Scan Architecture to Reduce Hardware Overhead

Presentation transcript:

Improved Random Pattern Delay Fault Coverage Using Inversion Test Points Soham Roy, Brandon Steine, Spencer Millican, Vishwani Agrawal Dept. of Electrical and Computer Engineering, Auburn University Auburn Research Student Symposium 2019, 04/09/2019 Motivation Conventional TP Architectures Test Point Insertion Method Circuit test: A critical part of the integrated circuit (IC) manufacturing process. Pseudo-random testing: Effective for detecting defects in previous generations of technology, but it’s utility is degraded. Test point insertion (TPI) developed to improve pseudo-random tests. Effectiveness of inversion-based test points (TPs) in lieu of traditional TPs by analyzing the delay and stuck-at fault coverage, which has not been examined by earlier studies on inversion TPs, is studied. This study does not propose a new TPI algorithm, and instead will use an established TPI algorithm. (H.-C. Tsai, K.-T. Cheng, C.-J. Lin and S. Bhawmik. A hybrid algorithm for * Test Point Selection for Scan-based BIST.* Proc. of 34th Design Automation Conference, pages 478-483,1997.). Algorithms use controllability and observability program (COP) to find the TP which maximizes fault coverage by calculating probability that each fault will be detected, depending on stuck-at 0 or stuck-at 1 fault model. Using industrial tools was infeasible since such tools are not programmed to give optimal inversion TP placement and would give favorable result towards conventional control TPs. The purpose of a TP is to make the excitation of faults and the observation of faults more likely under random stimulus. Pseudo-Random Testing Inversion-Based TP Architecture Results & Discussion Inversion TPs change signal value probabilities through inversions as opposed to forcing circuit lines to predetermined values. Inversion TPs excite both stuck-at 0 and stuck-at 1 faults when active. Inversion TPs excite and propagate delay faults when active. Inversion TPs may falter when a random signal needs to be less random. Stuck-at and transition delay fault coverage for ITC’99 and ISCAS’85 benchmarks. The conventional architecture decreases delay fault coverage significantly.