Device Engineering Team

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Presentation transcript:

Device Engineering Team SPICE Model Yoon-Jong Lee Sr. Manager Device Engineering Team

Contents 1. SPICE Model - Quality Assurance - 0.25um SPICE Model (aa2533C07.A) - 0.21um SPICE Model (aa1833C07.0) 2. Statistical Modeling 3. Interconnect Capacitance 4. Mixed Signal Characterization 5. TCAD Simulation

Device sizes for modeling Anam SPICE Model (Modeling from -55C to 150C) BSIM3v3.1 Device sizes for modeling (aa2533C07.A) Short Channel, Narrow Width Effects Non-Uniform Doping Effect Drain Induced Barrier Lowering Mobility Reduction with Gate and Substrate Bias Parasitic Source/Drain Resistance Better Fitting Accuracy at Near- Threshold Region for Analog Simulation

Quality Assurance of SPICE Model

0.25um SPICE Model (aa2533C07.A) NMOS Ids-Vds 11.98/0.25 VB=0V T=27C PMOS Ids-Vds 11.98/0.25 VB=0V T=27C NMOS Ids-Vgs 11.98/0.25 VD=0.1V T=27C PMOS Ids-Vgs 11.98/0.25 VD=-0.1V T=27C

0.21um SPICE Model (aa1833C07.0) NMOS Ids-Vds 16.6/0.21 VB=0V T=27 PMOS Ids-Vds 16.6/0.21 VB=0V T=27 NMOS Ids-Vgs 16.6/0.21 VD=0.1V T=27 PMOS Ids-Vgs 16.6/0.21 VB=-0.1V T=27

Threshold voltage vs. Gate length NMOS PMOS aa2533C07.A w/o Pocket NMOS PMOS aa1833C07.0 with Pocket

Temperature Characteristics of IDSAT NMOS Vdd=2.8V VB=0V PMOS Vdd=-2.8V VB=0V aa2533C07.A NMOS Vdd=2V VB=0V PMOS Vdd=-2V VB=0V aa1833C07.0

Gate Delay Time vs. Supply Voltage (aa2533C07.A)

Gate Delay Time vs. Temperature (aa1833C07.0) NMOS = 0.5/0.21um PMOS = 0.8/0.21um Fanout = 1

Process Parameter Distribution Mean=44.6 S. Dev. =0.36 Mean = 0.541 S. Dev.= 0.022 Mean = 43.5 S. Dev.= 0.37 Mean = -0.510 S. Dev.= 0.024

Sigma Contour Plot of 10/0.21um Device (aa1833C07.0) 420 440 460 480 500 520 540 140 160 180 200 220 240 IdsatP (uA/um) IdsatN (uA/um) SS FS FF SF TT 3σ 2σ

Interconnect Capacitance

Schematic of Test Pattern Ring Oscillator with Capacitance Loading Schematic of Test Pattern Metal 2 Line Wp/Lp=10/0.24 Wn/Ln=5/0.24 Metal 1 & 3 Plate Unit : [um]

Gate Delay Time vs. Supply Voltage (aa2533C07.A)

Mixed signal resistors ● aa2533C07.A

Mixed signal capacitors ● aa2533C07.A * Target value

( W : Gate width , L : Gate length ) MOSFET mismatch - aa2533C07.A Mismatch σ＝ A /√(W×L) ( W : Gate width , L : Gate length )

Parasitic pnp bipolar characteristics - aa2533C07.A Emitter size : 1 × 1 [um]

SIMS Profile Calibration I Channel & Well Profile (Boron) TCAD Simulation SIMS Profile Calibration I Channel & Well Profile (Boron)

SIMS Profile Calibration II MDD Profile (Arsenic) TCAD Simulation SIMS Profile Calibration II MDD Profile (Arsenic)

SIMS Profile Calibration III S/D Profile (Arsenic & Phosphorous) TCAD Simulation SIMS Profile Calibration III S/D Profile (Arsenic & Phosphorous)

TCAD Simulation Simulated & Measured I-V Characteristics Ids vs. Vgs of 0.21㎛ NMOS Ids vs. Vds of 0.21㎛ NMOS