Valter Bonvicini, Giulio Orzan, Nicola Zampa, Gianluigi Zampa

Slides:



Advertisements
Similar presentations
1 ACTAR meeting – Santiago March 2008 Requirements Features required not available in standard ASICs for HEP: Auto-triggerable. Large dynamic range. Low.
Advertisements

R&D for ECAL VFE technology prototype -Gerard Bohner -Jacques Lecoq -Samuel Manen LPC Clermond-Ferrand, Fr -Christophe de La Taille -Julien Fleury -Gisèle.
SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.
18/05/2015 Calice meeting Prague Status Report on ADC LPC ILC Group.
Front-end electronics for Time Projection Chamber I.Konorov Outlook:  TPC requirements  TPC readout options  Options for TPC FE chips  Prototype TPC.
ACTAR Nov 05 Lolly Pollacco CEA Saclay Front End Electronics for ACTAR.
RSH Front End Electronic R. Beaujean, S. Böttcher Kiel Nov 07, 2005.
Development of Readout ASIC for FPCCD Vertex Detector 01 October 2009 Kennosuke.Itagaki Tohoku University.
MR (7/7/05) T2K electronics Beam structure ~ 8 (9?) bunches / spill bunch width ~ 60 nsec bunch separation ~ 600 nsec spill duration ~ 5  sec Time between.
P. Baron CEA IRFU/SEDI/LDEFACTAR Meeting Santiago de Compostela March 11, A review of AFTER+ chip Its expected requirements At this time, AFTER+
L.ROYER – TWEPP Oxford – Sept The chip Signal processing for High Granularity Calorimeter (Si-W ILC) L.Royer, J.Bonnard, S.Manen, X.Soumpholphakdy.
Hold signal Variable Gain Preamp. Variable Slow Shaper S&H Bipolar Fast Shaper 64Trigger outputs Gain correction (6 bits/channel) discriminator threshold.
Development of the Readout ASIC for Muon Chambers E. Atkin, I. Bulbalkov, A. Voronin, V. Ivanov, P. Ivanov, E. Malankin, D. Normanov, V. Samsonov, V. Shumikhin,
65 nm CMOS analog front-end for pixel detectors at the HL-LHC
1 Luciano Musa, Gerd Trampitsch A General Purpose Charge Readout Chip for TPC Applications Munich, 19 October 2006 Luciano Musa Gerd Trampitsch.
Gianluigi Zampa Santa Fe, NM, USA June 23, 2004 Silicon Tungsten Calorimeters The WIZARD experiments – PART II – OUTLINE The PAMELA Si-W calorimeter electronics.
ICPPA-2015 Moscow Oct ASIC for calorimetric measurements in astrophysical experiment NUCLEON (overview) E. Atkin1, A. Voronin1,2, D. Karmanov2,
L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.
1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN.
ASIC Activities for the PANDA GSI Peter Wieczorek.
LHCb Calorimeter Upgrade Meeting – 10th September 2012 – CERN LHCb Calorimeter Upgrade Electronics: ASIC solution status E. Picatoste, D. Gascon Universitat.
SKIROC ADC measurements and cyclic ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting Orsay June.
S. Bota – Calorimeter Electronics overview - July 2002 Status of SPD electronics Very Front End Review of ASIC runs What’s new: RUN 4 and 5 Next Actions.
1 19 th January 2009 M. Mager - L. Musa Charge Readout Chip Development & System Level Considerations.
VMM Update Front End ASIC for the ATLAS Muon Upgrade V. Polychronakos BNL RD51 - V. Polychronakos, BNL10/15/131.
CBM 12 th Meeting, October 14-18, 2008, Dubna Present status of the first version of NIHAM TRD-FEE analogic CHIP Vasile Catanescu and Mihai Petrovici NIHAM.
Front-end Electronic for the CALICE ECAL Physic Prototype Christophe de La Taille Julien Fleury Gisèle Martin-Chassard Front-end Electronic for the CALICE.
CSNSM SPACIROC S. Ahmad, P. Barrillon, S. Blin, S. Dagoret, F. Dulucq, C. de La Taille IN2P3-OMEGA LAL Orsay, France Y. Kawasaki - RIKEN,Japan I. Hirokazu.
Flex Cable Readout unit Si Sensor 256 analog lines Interconnect board NCC signal packaging concept PA board -This is the calorimeter – all pads in the.
VFE & PCB Status & schedule of production Presented by Julien Fleury Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard.
CALOCUBE SVILUPPO DI CALORIMETRIA OMOGENEA AD ALTA ACCETTANZA PER ESPERIMENTI DI RAGGI COSMICI NELLO SPAZIO Call nell’ambito della CSN5 dell’INFN Oscar.
1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting London 2008.
SKIROC status Calice meeting – Kobe – 10/05/2007.
The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT 1 INFN Sezione di Pavia I Pavia, Italy.
Transient Waveform Recording Utilizing TARGET7 ASIC
A 12-bit low-power ADC for SKIROC
KLOE II Inner Tracker FEE
Journées VLSI-FPGA-PCB Juin 2010 Xiaochao Fang
Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011
A General Purpose Charge Readout Chip for TPC Applications
ECAL front-end electronic status
The Gamma-400 MISSION Valter Bonvicini INFN – Trieste, Italy
2^ CaloCube meeting Firenze, 20 Febbraio 2015 Oscar Adriani
Idee per lo sviluppo del Charge Identifier
ASIC PMm2 Pierre BARRILLON, Sylvie BLIN, Selma CONFORTI,
on behalf of the AGH and UJ PANDA groups
Analog FE circuitry simulation
Design of the 64-channel ASIC: status
96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output
A Readout Electronics System for GEM Detectors
Development of sensors and electronics for the cubic calorimeter
Multi-Anode ReadOut Chip for MaPMTs: MAROC3 MEASUREMENTS
TDC at OMEGA I will talk about SPACIROC asic
CALICE COLLABORATION LPC Clermont LAL Orsay Samuel MANEN Julien FLEURY
Electronics for the E-CAL physics prototype
A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS
EUDET – LPC- Clermont VFE Electronics
Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard
Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard
Charge measurement of STK
PID electronics for FDIRC (Focusing Detector of Internally Reflected Cherenkov light) and FTOF (Forward Time of Flight) Christophe Beigbeder and Dominique.
BESIII EMC electronics
SKIROC status Calice meeting – Kobe – 10/05/2007.
On behalf of CEPC calorimeter working group
Turning photons into bits in the cold
Signal processing for High Granularity Calorimeter
ASPID (Application of Silicon Photomultipliers to Imaging Detectors)
Presented by T. Suomijärvi
Ongoing R&D in Orsay/Saclay on ps time measurement: status of the USB-powered 2-channel 3.2GS/s 12-bit digitizer D.Breton & J.Maalmi (LAL Orsay), E.Delagnes.
Readout Electronics for Pixel Sensors
Presentation transcript:

Valter Bonvicini, Giulio Orzan, Nicola Zampa, Gianluigi Zampa Aggiornamento sullo sviluppo di una nuova versione del chip CASIS per CALOCUBE Valter Bonvicini, Giulio Orzan, Nicola Zampa, Gianluigi Zampa INFN Trieste CALOCUBE meeting Firenze, 20 giugno 2014

Front-end electronics (a big challenge…) Scientific interest: direct measurement of the cosmic-ray fluxes above the TeV region. Examples: Direct observation of cosmic-ray electrons up to 10 TeV Measurement of cosmic-ray nuclei flux and elemental composition up to the “knee” ( 1014 – 10 15 eV) A major concern: dynamic range!!! (with sensitivity down to fractions of a MIP) 06/20/2014 V. Bonvicini - CaloCube

Front-end electronics R&D carried on in Trieste through the CSN 5 experiments CASIS and CASIS2 Several prototypes designed, realized and tested CASIS1.2A ASIC (used for the prototypes of calorimeters realized in Florence): Double-gain (double-range) CSA Double-correlated sampling, MUX and output buffer Input calibration circuit (with arbitrary channel pattern) 16 channels Noise: 2700 e- + 8e-/pF Power consumption: 2.8 mW/channel Dynamic range (low gain): 53 pC 06/20/2014 V. Bonvicini - CaloCube

Next step: CASIS1.2B 16 FE channels with A/D conversion 5300 µm 4000 µm 16 FE channels with A/D conversion function integrated in the ASIC; 1 12-bit cyclic ADC /channel with capacitor averaging and digital correction; Design submitted in August 2013 (prototypes arrived at the end of 2013); 06/20/2014 V. Bonvicini - CaloCube

CASIS1.2B: layout of a complete channel 06/20/2014 V. Bonvicini - CaloCube

CASIS1.2B Details of one chip (AMS 0.35 um CMOS C35B4 technology) 06/20/2014 V. Bonvicini - CaloCube

CASIS1.2B Detail of the test boards designed and realized in Trieste for the characterization of the new ASIC 06/20/2014 V. Bonvicini - CaloCube

CASIS1.2B CASIS1.2B chip in “Daughter board” CQFP120 package “Mother board” 06/20/2014 V. Bonvicini - CaloCube

CASIS1.2B Test set-up in Trieste 06/20/2014 V. Bonvicini - CaloCube