New UK-Planar Pixel mask G. Casse EVO meeting 08/08/21

Outline We gave the quad mask, successfully processed and bonded. Rerun is happening for improving VBD characteristics. Also, lower resistivity Silicon could be used. New mask is needed for trying new-geometries for the forward (UK main interest as hardware contribution to the whole project). This new mask will have new geometries, but I also propose to try on it new solutions (possibly rather adventurous) of interest for pixel connection to electronics. I think that the new solutions can be implemented as extra steps (special masks to add during the processing. If left out, usual pixel processing business....). EVO meeting 08/08/21

New geometries and solutions QUAD Mask Sensor type: SC1, SC2 – “test” 450 µm edge. SC3, SC4 – 500x25, 450 µm edge. SC5 – SC8 “test”, 300 µm edge. SC6 – SC7 “production”, 300 µm edge. QUAD1 – “production”, 450 µm edge. QUAD2 – “test”, 300 µm edge. QUAD3 – “test”, 450 µm edge. QUAD4 – “test”, 450 µm edge. QUAD5 – “production” 450 µm. New geometries and solutions Proposed geometries: Slim elongated: 25x500, 25x2000, 50x2000. Square FE-I4 density. Square reduced density. Proposed biasing solutions: Biasing dots (Std) Poly-resistors AC coupling metal AC coupling doped poly (enhanced AC coupling?). EVO meeting 08/08/21

Geometries Possible pixel geometries based around a FE-I4 footprint. 25x500 µm2 50x2000 µm2 25x2000 µm2 125x167 µm2 100x125 µm2 EVO meeting 08/08/21

Use of FE-I4 channels Type Channel reduction factor 125x167 µm2 1.67 8 EVO meeting 08/08/21

Biasing Individual P-spray Common Example from HPK (note, error in the dot biasing, you need half of the number of dots.... HPK only tried it for biasing purposes. BUT: with poly bias it is possible to AC couple the pixels to the ROC. BIG drawback: weak value for the AC coupling. Would need very small dielectric thickness. EVO meeting 08/08/21

Biasing Try with poly + AC coupling. Coupling with : metal only and high-doped poly with metal. Gianluigi to investigate issues with Micron. Proposal: ½ wafer dedicated to standard processing with the different geometries. ½ wafer dedicated to special processing with poly (resistors and capacitive plates). EVO meeting 08/08/21