Southern Illinois University Edwardsville Development of a Multi-Channel Integrated Circuit for Use in Nuclear Physics Experiments Where Particle Identification is Important Michael Hall Southern Illinois University Edwardsville IC Design Research Laboratory April 3, 2007

Design Team Southern Illinois University Edwardsville: Dr. George Engel (PI) Michael Hall (graduate student) Justin Proctor (graduate student) Venkata Tirumasaletty (graduate student) Washington University in St. Louis: Dr. Lee Sobotka (Co-PI) Jon Elson (electronics specialist) Dr. Robert Charity Western Michigan: Dr. Mike Famiano (Co-PI)

Research Objective Design a custom microchip which can be used by nuclear physicists when they perform experiments. In these experiments, physicists use detectors to sense radiation. These experiments often require that the physicists identify the type of radiation (α particle, γ-ray, etc) that struck the detector.

NSF Proposal (Funded) $200,000 grant funded from September 2006 to August 2008. Design, simulate, and fabricate a custom integrated circuit for particle identification suitable for use with CsI(Tl) (used for charge-particle discrimination) Liquid Scintillator (used for neutron-gamma discrimination) 8 channel “prototype” chip 16 channel “production” chip We propose to design, extensively simulate, and fabricate a PSD chip suitable for use with both CsI(Tl) (used for charge-particle discrimination) and liquid scintillator (used for neutron-gamma discrimination). The IC will require no active cooling. An 8-channel “prototype” chip will be submitted for fabrication within 8 months of funding being approved and a revised, 16-channel “production” version will be submitted after use of the “prototype” IC in the experiment planned for the summer of 2007. The “production” chip will address any deficiencies uncovered in the initial “prototype” and will be made available to other groups.

Intended Applications The chip will be used in an experiment at the National Superconducting Cyclotron Laboratory (NSCL) in Fall 2007 by Washington University collaborators. Mass production of PSD technology is actively being sought by our government’s Department of Homeland Security. The integrated circuit (IC ) will be suitable for use in recently planned nuclear physics experiments. One has already been approved by the National Superconducting Cyclotron Laboratory (NSCL). The experiment is to be performed in Fall of 2007. The microchip currently under design uses a technique known as pulse shape discrimination (PSD) to classify the radiation type (i.e. a particle, g-ray, etc.). Our research has the potential to greatly reduced false positives from detectors sensitive to different types of radiation. While circuits capable of particle identification are available in discrete analog form (bulky!) and in digital form (power-hungry!), it is not available in a low-power, small, integrated form. As a result, mass production of PSD technology (at a reasonable) is currently unavailable, but is actively being sought by our government’s Department of Homeland Security. Our IC may someday play an important role in the detection of nuclear attacks launched by terrorists against our nation!

HiRA Detector Array at MSU Chip and Sensor Array HiRA Detector Array at MSU Earlier IC developed in our lab currently being used in Physics experiments around the country

Simulated Input Pulse for CsI(Tl) Detector Integrators A 0 to 400 ns B 1500 to 1500 ns C 0 to 9000 ns Integration periods at the beginning of the signal are assumed to start before the pulse (at -5 ns).

Need for an Integrated Circuit Particle identification (α particle, γ-ray, etc.) capability Ability to support multiple (i.e. initially eight but eventually sixteen) radiation detectors Three separate integration regions with independent control of charging rate in each region which can be used for high-quality pulse shape discrimination (PSD). Built-in high-quality timing circuitry Multiple (3) triggering modes Data sparsification

Overview of PSD System Detector (PMT or photodiode) External discriminators (CFDs) External delay lines so we can start integrations before arrival of pulse External control voltages determine Delay and Width of integration periods Outputs A, B, C integrator voltages and relative time, T

Channel 3 on-chip sub-channels for integrators A, B, C Delay and width of integrators set by externally supplied control voltages Timing relative to a common stop signal

Sub-Channel

Pulse Shape Discrimination Plot for CsI(Tl) Detector Detector: CsI(Tl) Integrators: A, B Energy Max: 100 MeV (for 2V at input of integrator) Energy Range: 1 – 100 MeV Includes all noise sources

Angular PSD Plots (CsI) Detector: CsI(Tl) Integrators: A, B Energy Max: 100 MeV Energy Range: 1 – 100 MeV 5000 realizations Includes all noise sources

Current Work Circuit design and simulations Behavioral level simulations (VerilogA) to verify functionality of one complete channel including read-out electronics

Future Work Layout Fabrication Testing of the IC Chip should leave for fabrication in August 2007. Will take approximately 2 months to make. Testing of the IC Chip will be used in experiment at NSCL in Fall 2007