RTL Design Methodology Lecture 15 RTL Design Methodology min_max_avr example

Structure of a Typical Digital System Data Inputs Control Inputs Control Signals Datapath (Execution Unit) Controller (Control Unit) Status Signals Data Outputs Control Outputs

Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block diagram Block diagram State diagram or ASM chart VHDL code VHDL code VHDL code

Steps of the Design Process Text description Interface Pseudocode Block diagram of the Datapath Interface divided into Datapath and Controller ASM chart of the Controller RTL VHDL code of the Datapath, Controller, and Top-Level Unit Testbench for the Datapath, Controller, and Top-Level Unit Functional simulation and debugging Synthesis and post-synthesis simulation Implementation and timing simulation Experimental testing using FPGA board

Steps of the Design Process Introduced in Class Today Text description Interface Pseudocode Block diagram of the Datapath Interface divided into Datapath and Controller ASM chart of the Controller RTL VHDL code of the Datapath, Controller, and Top-level Unit Testbench for the Datapath, Controller, and Top-Level Unit Functional simulation and debugging Synthesis and post-synthesis simulation Implementation and timing simulation Experimental testing using FPGA board

min_max_average example

Circuit Interface clk DONE reset n n in_data out_data 5 MIN_MAX_AVR in_addr 2 out_addr write START

Interface Table Port Width Meaning clk 1 System clock reset System reset – clears internal registers in_data n Input data bus in_addr 5 Address of the internal memory where input data is stored write Synchronous write control signal START Starts the computations DONE Asserted when all results are ready out_data Output data bus used to read results out_addr 2 01 – reading minimum 10 – reading maximum 11 – reading average

Pseudocode Begin: MAX = 0; MIN = 2n-1; SUM = 0; for i=0 to 31 do wait for START; MAX = 0; MIN = 2n-1; SUM = 0; for i=0 to 31 do CDATA = M[i]; SUM = SUM + CDATA; if (CDATA < MIN) then MIN = CDATA; endif if (CDATA > MAX) then MAX = CDATA; endfor AVR = SUM/32 DONE = 1 goto Begin