Lecture 23

DMA Cascading

DMA Programming Model DMA has 4 – Channels Each Channel can be programmed to transfer a block of maximum size of 64k. For each Channel there is a Base Register Count Register Higher Address Nibble/Byte is placed in Latch B. The Mode register is conveyed which Channel is to be programmed and for what purpose i.e. Read Cycle, Write Cycle, Memory to memory transfer. A request to DMA is made to start it’s transfer.

Internal Registers No of 16 & 8 bit Internal registers Total of 27 internal registers in DMA Register Number Width Starting Address 4 16 Counter 4 16 Current Address 4 16 Current Counter 4 16 Temporary Address 1 16 Temporary Counter 1 16 Status 1 8 Command 1 8 Intermediate Memory 1 8 Mode 4 8 Mask 1 8 Request 1 8

DMA Modes Block Transfer Single Transfer Demand Transfer

DMA Status Register

DMA Command Register