CS203 – Advanced Computer Architecture

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Presentation transcript:

CS203 – Advanced Computer Architecture Tomasulo Algorithm

Cycle 1: LD1 – Issue/GenAddr ADD F6, F8, F2 DIV F10, F0, F6 SUB F8, F6, F2 MLT F0, F2, F4 LD F2, 45(R3) LD F6, 34(R2)

Cycle 2: LD1 – LD Buffer LD2 – Issue/GenAddr ADD F6, F8, F2 DIV F10, F0, F6 SUB F8, F6, F2 MLT F0, F2, F4 LD F2, 45(R3) LD F6, 34(R2)

Cycle 3: LD1 – Loading LD2 – LD Buffer MUL – Issue/Wait on F2 ADD F6, F8, F2 DIV F10, F0, F6 SUB F8, F6, F2 MLT F0, F2, F4 LD F2, 45(R3) LD F6, 34(R2)

Cycle 4: LD1 – Broadcast CDB LD2 – Loading MUL – Wait on F2 SUB – Issue/Wait on F2 ADD F6, F8, F2 DIV F10, F0, F6 SUB F8, F6, F2 LD F2, 45(R3) MLT F0, F2, F4 LD F6, 34(R2)

Cycle 5: LD2 – Broadcast CDB MUL – F2 Ready/ Exec SUB – F2 Ready/ Exec DIV – Issue/ Wait on F0 ADD F6, F8, F2 DIV F10, F0, F6 MLT F0, F2, F4 SUB F8, F6, F2 LD F2, 45(R3)

Cycle 6: MUL –Exec SUB –Exec DIV – Wait on F0 Add – Issue/ Wait on F8 ADD F6, F8, F2 DIV F10, F0, F6 SUB F8, F6, F2 MLT F0, F2, F4

Cycle 7: MUL –Exec SUB – Exec Done DIV – Wait on F0 Add – Wait on F8 DIV F10, F0, F6 ADD F6, F8, F2 SUB F8, F6, F2 MLT F0, F2, F4

Cycle 8: MUL –Exec SUB – Broadcast CDB DIV – Wait on F0 Add – F8 Ready/ Exec DIV F10, F0, F6 ADD F6, F8, F2 SUB F8, F6, F2 MLT F0, F2, F4

Cycle 9: MUL –Exec DIV – Wait on F0 Add – Exec DIV F10, F0, F6 ADD F6, F8, F2 MLT F0, F2, F4

Cycle 10: MUL –Exec DIV – Wait on F0 Add – Exec Done DIV F10, F0, F6 ADD F6, F8, F2 MLT F0, F2, F4

Cycle 11: MUL –Exec DIV – Wait on F0 Add – Broadcast CDB Note: We don’t overwrite F6, because F6 value from LD1 was buffered in the RS at Issue (Cycle 5) DIV F10, F0, F6 ADD F6, F8, F2 MLT F0, F2, F4

Cycle 12-14: MUL –Exec DIV – Wait on F0 Cycle 15: MUL –Exec Done DIV F10, F0, F6 MLT F0, F2, F4

Cycle 16: MUL – Broadcast CDB DIV – F0 Ready/ Exec DIV F10, F0, F6 MLT F0, F2, F4

Cycle 17-55: DIV – Exec Cycle 56: DIV – Exec Done DIV F10, F0, F6

Cycle 57: DIV – Broadcast CDB DIV F10, F0, F6