Processor Design Datapath and Design

All tables and diagrams in this presentation are from: D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Third Edition (The Morgan Kaufmann Series in Computer Architecture and Design), Morgan Kaufmann, 2002.

Datapath

Basic Functional Units

Instruction Sequencing

Operations on Data in Registers

Registers and Memory

Simple Implementation Scheme Single cycle Implementation

ALU Conttrol

Control Signals

R-format and I-format Instructions

Control Signals and Instruction Opcode

Control Function

Multicycle Implementation

Intstruction fetch IR <= Memory[PC]; PC <= PC+4 IR <= Memory[PC]; PC <= PC+4

IorD = 0 MemRead = 1 IRWrite = 1 IR <= Memory[PC];

PC <= PC+4 PCSource = 01 PCWrite = 1 ALUOp = 00 ALUSrcB = 01 ALUSrcA = 0 PC <= PC+4

Intstruction decode/register fetch A <= Reg[ IR [25:21] ]; B <= Reg[ IR [20:16] ]; ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 ) A <= Reg[ IR [25:21] ]; B <= Reg[ IR [20:16] ]; ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 )

A <= Reg[ IR [25:21] ]; B <= Reg[ IR [20:16] ];

ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 ) ALUOp = 00 ALUSrcB = 11 ALUSrcA = 0 ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 )

R-type instruction ALUOut <= A op B Reg[ IR[15:11] ] <= ALUOut ALUOut <= A op B Reg[ IR[15:11] ] <= ALUOut

ALUOp = ?? ALUSrcB = 0 ALUSrcA = 1 ALUOut <= A op B

Reg[ IR[15:11] ] <= ALUOut RegWrite = 1 MemtoReg = 0 RegDst = 1 Reg[ IR[15:11] ] <= ALUOut

Load instruction ALUOut <= A + SignExt(IR[15:0]) MDR <= Memory[ALUOUT] Reg[IR[20:16] ] <= MDR ALUOut <= A + SignExt(IR[15:0]) MDR <= Memory[ALUOUT] Reg[IR[20:16] ] <= MDR

ALUOut <= A + SignExt(IR[15:0]) ALUOp = 00 ALUSrcB = 10 ALUSrcA = 1 ALUOut <= A + SignExt(IR[15:0])

MDR <= Memory[ALUOUT] ; Reg[IR[20:16] ] <= MDR IorD =1 MemRead =1 MemtoReg =1 RegWrite =1 RegDst = 0 MDR <= Memory[ALUOUT] ; Reg[IR[20:16] ] <= MDR