STT-RAM Design Fengbo Ren Advisor: Prof. Dejan Marković Dec. 3rd, 2010 Progress Update STT-RAM Design Fengbo Ren Advisor: Prof. Dejan Marković Dec. 3rd, 2010

Background STT-RAM: Spin Transfer Torque Random Access Memory Key memory device: magnetic tunnel junctions (MTJ) R/W circuit: CMOS Most existing memory technology is greatly challenged beyond 45 nm SRAM: high power consumption, leakage increasing 10X with each technology node DRAM: refresh current increasing, capacitor element hardly can maintain the necessary charge. Flash: limited endurance, high write power, very slow write speed. Need for universal memory Parallel Anti-parallel RP RAP STT-RAM (spin-transfer torque random access memory) is a revolutionary new memory technology, derived from Grandis' pioneering research in Spintronics,

Memory Technology Comparison STT-RAM combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, the non-volatility of Flash, and essentially unlimited endurance. that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, the non-volatility of Flash, and essentially unlimited endurance. It has superior write selectivity, excellent scalability beyond 32 nm technology node, low power consumption, and a simpler architecture and manufacturing process than first-generation MRAM. In this presentation, we will review the current status of the STT-RAM technology and devices, discuss key challenges, and outline future potential applications and products. It is this combination of features that some suggest make it the "universal memory", able to replace SRAM, DRAM, EEPROM and flash. This also explains the huge amount of research being carried out into developing it.

Cell Size Cell structure 2T-1MTJ 1T-1MTJ 1T-N MTJ??

MTJ Sharing Problem Unexpected DC current paths through every MTJ. Accidental switching in R/W Parasitic resistance in parallel with the accessed MTJ Reading error Conclusion Not going to work if M>2, M is # of MTJs shared by transistor M = 2, N>8, significant TMR degradation When RP = 500Ω, TMR = 120%, M = 2, N = 4 TMR’ = 45%, might be able to read. MTJ with higher RP and TMR, error correction coding will help 1T-1MTJ & MTJ-sharing (M=2, N=64) memory arrays are implemented.

Cell size (Norm. to SRAM) 1T-1MTJ Memory Cell Layout view Min cell size (constrained by design rule) F is min. space between x1 metal wire 65-nm 45-nm 65-nm 45-nm M4 0.55 um C1 0.405 um 0.5 um 0.38 um 65-nm 45-nm Cell area (um2) 0.275 0.1539 Feature size (um) 0.1 0.07 Cell size (F2) 27.5 31.4 Cell size (Norm. to SRAM) 1 0.12-0.2 0.2 0.1 0.3-0.68 0.32-0.8 0.12-0.24 0.12-0.4 Customized SRAM cell area (um2) 2.52 1.596

Write P->AP Vgs_P = VWL - Vdrop ≈ VDDW Vds_P = VDDW – Vdrop – Vmtj_P AP->P Vgs_AP = VWL – Vdrop – Vmtj_AP Vds_AP = VDDW - Vdrop – Vmtj_AP Boosting VWL Limited by Vgs_P (0.1 V margin) Boosting VDDW Limited by Vds_AP (0.5-0.6 V margin) Have to use thicker oxide devices in the write driver circuit (in red)

Write Current Comparison Compare 3 cases of boosting voltage Constraints VDDW < VDDmax Vgs, Vds < VDDmax For all devices Rp = 744 Ω Ref Case 1 Case 2 Case 3 FET in array Thin Oxide Lvt FET in write driver Thin Oxide Rvt Medium Oxide 1.5V high-speed IO Thick Oxide 1.8V regular IO VDDmax (V) 1.1 1.65 1.98 VDDW (V) 1 ABAP VWL (V)

Write Current Comparison Result Boost up VDDW to 1.1V, VWL to max - 21-22% gain Boost up VDDW to 1.5V, VWL to max - 30-33% gain Medium oxide device used, 2.2x bigger write driver Boost up VDDW to 1.9V, VWL to max - 35-37% gain Thick oxide device used, 7.6x bigger write driver Rp = 744 Ω Ref Case 1 Case 2 Case 3 VWL (V) 1 1.17 1.23 1.3 VDDW (V) 1.1 1.65 1.9 Vds (V) P->AP 0.42 0.38 0.66 0.78 AP->P 0.57 0.55 0.95 Vgs (V) 0.93 1.09 0.6 0.63 Iw (uA) 585 739 868 925 210 270 301 325 Area Overhead 1x 4.4x 35x I Gain v.s. Ref 26% 48%/17% 58%/7% 29% 43%/11% 55%/8%

Boost up VDDW If thin oxide devices are used in write driver Can not meet Vds constraint! Medium oxide devices have to be used in write driver and mux. So case 2 is the best, case 3 has too much area overhead

Boost up VWL, dual VWL (VWL_P , VWL_AP) On the addressed WL, cells on un-addressed column can not meet Vgs constraint BL and SL of un-read/write column have to be kept on a positive voltage level of Vidle.

Result after boosting VDDW & VWL Medium oxide 1.5V high-speed IO device used in write driver, VDDW = 1.65V Vidle = Vprecharge = 0.55V Support VWL boosting up to 1.65V Rp = 744 Ω Ref Boost 1 Boost 2 Vidle (V) 0.55 0.9 VWL_P/VWL_AP (V) 1.1/1.1 1.23/1.65 1.23/2 Vds (V) P->AP 0.78 0.66 AP->P 1 0.67 0.45 Vgs (V) 0.98 1.1 0.58 0.8 0.94 Iw (uA) 585 867 210 440 550 I Gain v.s. Ref 48% 110% 157%