Full Profile CMP Metrology

Slides:



Advertisements
Similar presentations
Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.
Advertisements

SEM Magnification Calibration. Magnification Errors Proper calibration of the SEM scans (magnification) is primary to metrology. SEM Magnification requires.
Accelerating Productization. Functional Metrology TM Challenges of Semiconductor Productization Leading IDM’s Solution Novel Solution -> In-product Functional.
Characterizing the Nanoscale Layers of Tomorrow’s Electronics : An Application of Fourier Analysis Chris Payne In Collaboration With: Apurva Mehta & Matt.
How a chip is made November 15, 2011.
Consortium for Metrology of Semiconductor Nanodefects Mechanical Engineering Consortium for Metrology of Semiconductor Nanodefects Semi-Annual Research.
BCAM 1 A Physically Based Model for Predicting Volume Shrinkage in Chemically Amplified Resists Nickhil Jakatdar, Junwei Bao, Costas Spanos University.
Impact of Nanotopography on STI CMP in Future Technologies D. Boning and B. Lee, MIT N. Poduje, ADE Corp. J. Valley, ADE Phase-Shift W. Baylies, Baytech.
PUT JOSH WEB- STREAM HERE. 4/30/2010 Iowa State University EE492 – Senior Design II.
Copper CMP Planarization Length - MRS April 19 th, 2001 – Paul Lefevre – Page 1 DIRECT MEASUREMENT OF PLANARIZATION LENGTH FOR COPPER CHEMICAL MECHANICAL.
8:30 – 9:00Research and Educational Objectives / Spanos 9:00 – 9:45 CMP / Doyle, Dornfeld, Talbot, Spanos 9:45 – 10:30 Plasma & Diffusion / Graves, Lieberman,
Metallization: Contact to devices, interconnections between devices and to external Signal (V or I) intensity and speed (frequency response, delay)
Scatterfield Zero Order Imaging
II-Lithography Fall 2013 Prof. Marc Madou MSTB 120
11/8/ Chemical Aspects of CMP SFR Workshop November 8, 2000 Tanuja Gopal and Prof. Jan Talbot UC San Diego La Jolla, CA 2001 GOAL: Build integrated.
MIT Lincoln Laboratory NU Status-1 JAB 11/20/2015 Advanced Photodiode Development 7 April, 2000 James A. Burns ll.mit.edu.
Fixed Abrasive Design for Chemical Mechanical Polishing
11/8/ Microplasma Optical Emission Spectrometer (MOES) on a chip SFR Workshop November 8, 2000 Michiel Krüger, David Hsu, Scott Eitapence, K. Poolla,
11/8/ Sensitivity of Spectroscopic Scatterometry: Sub-100nm Technology SFR Workshop November 8, 2000 Ralph Foong, Costas Spanos Berkeley, CA 2001.
Small Feature Reproducibility. 11/8/99 SFR Workshop - Overview 2 Small Feature Reproducibility Measuring, Understanding and Controlling Variability in.
Andrew Chang, David Dornfeld
Design For Manufacturability in Nanometer Era
Introduction to Silicon Processing Dr Vinod V. Thomas SMIEEE Ref: Section 2.2 ASICs : MJS Smith.
Acoustic and Thermal Methods in Detecting Endpoint during Chemical Mechanical Polishing of Metal Overlay for Nanoscale Integrated Circuits Manufacturing.
Date of download: 6/2/2016 Copyright © 2016 SPIE. All rights reserved. Metrology quality and capability association to the profitability. Figure Legend:
Feature-level Compensation & Control F LCC Lithography April 5, 2006 A UC Discovery Project.
Date of download: 7/8/2016 Copyright © 2016 SPIE. All rights reserved. Points are the nominal spot locations on the calibration standard and the test specimen.
5/24/ Small Feature Reproducibility Educational Activities N. Cheung, D. Dornfeld, D. Graves, M. Lieberman, C. Spanos SFR Workshop May 24, 2001 Berkeley,
Surface Treatment Solutions for Low-k Dielectrics
LIGHT BACKSCATTERING ANALYSIS of Textured Silicon SAMPLES
Wisconsin Center for Applied Microelectronics
Automated Characterization of Optical Image Quality
Automated Characterization of Optical Image Quality
On Wafer Ion Flux Sensors
Figure 1.1 A silicon wafer. Figure 1.1 A silicon wafer.
Figure 1.1. A silicon wafer..
Prof. Jang-Ung Park (박장웅)
Presentation Outline Introduction to Chapman Instruments
Brian Tang and Duane Boning MIT Microsystems Technology Laboratories
Layout and fabrication of CMOS circuits
BY SURAJ MENON S7,EEE,61.
Technology advancement in computer architecture
3rd Annual SFR Workshop & Review, May 24, 2001
Nanoscale Dielectric Films by Plasma Oxidation
CHE 5480 Summer 2005 Maricel Marquez
Sensitivity of Spectroscopic Scatterometry: Sub-100nm Technology
Andrew Chang, David Dornfeld
3rd Annual SFR Workshop, November 8, 2000
Measure the width of date and D on a dime
Overview of VLSI 魏凱城 彰化師範大學資工系.
Section 9: CMP EE143 – Ali Javey.
Lithography Diagnostics Based on Empirical Modeling
Resist Resolution Enhancement and Line-end Shortening Simulation
Layer Transfer Using Plasma Processing for SMART-Wafer
Enabling Full Profile CMP Metrology and Modeling
SILICON MICROMACHINING
Autonomous temperature sensor for bake plate calibration
Profile Extraction with Specular Spectroscopic Scatterometry
Process Recipe Optimization using Calibrated Simulation Engine
Plasma Chamber Spectrographic Data Acquisition and Archival
Resist Resolution Enhancement and Line-end Shortening Simulation
Acoustic Emission Sensing for Chemical Mechanical Polishing (CMP)
Scratch Testing of Silicon Wafers for Surface Characterization
Resist modeling, Simulation and Line-End Shortening effects
Jianfeng Luo, Prof. David Dornfeld
Junwei Bao, Costas Spanos
Effects of LER on MOSFET Electrical Behavior
Jianfeng Luo and David A. Dornfeld
Jianfeng Luo, David Dornfeld
Presentation transcript:

Full Profile CMP Metrology SFR Workshop November 8, 2000 Runzi Chang, Costas Spanos Berkeley, CA 2001 GOAL: Develop periodic grating metrology to support integrated CMP model (with Dornfeld and Talbot) 11/8/2000

Motivation CMP is an enabling technology for the semiconductor industry in its drive toward gigabit chips and sub-180nm feature sizes Non-uniformity problems on patterned wafers Depth of focus problem on lithography High resistance interconnect degrades circuit performance The first principal model can help optimize the operation of CMP and drive the technology further in the long run 11/8/2000

Key idea Oxide Substrate Use Scatterometry to monitor the profile evolution The results can be used for better CMP modeling 11/8/2000

Mask Design The size of the metrology cell is 250m by 250m 2m pitch with 50% pattern density 11/8/2000

Sensitivity of Scatterometry (GTK simulation) We simulated 1 mm feature size, 2 mm pitch and 500nm initial step height, as it polishes. The simulation shows that the response difference was fairly strong and detectable. 11/8/2000

Current Status Done mask design and processing in the Lab, some proof-of concept wafers are ready to polish Before the characterization experiments, we would like to know Is the scattermeter signal sensitive to the profile evolution? Answer: yes. How does the initial profile look like? LEO (SEM) can give a cross section view (we need to cut the wafer, then can’t do CMP on this wafer anymore!) AFM can give a smooth profile (but it needs some calibration) 11/8/2000

Comparison of LEO and AFM measurements They are similar except that the height from LEO is smaller due to some tilt at the measurement We’re calling help for a well calibrated AFM 11/8/2000

Next Step Do measurements using Sopra for the initial structures, compare results with the AFM measurements Build an electromagnetic response library Design experiments, polish finished wafers and do scatterometry measurements Collect AFM measurements in order to refine the library 11/8/2000

2002 and 2003 Goals Integrate initial chemical models into basic CMP model; Validate predicted pattern development (with Dornfeld and Talbot), by 8/31/2002. Develop comprehensive chemical and mechanical model (with Dornfeld and Talbot); Perform experimental and metrological validation , by 8/31/2003. 11/8/2000