Year One Report (part 1 of 2): Models to Enable System-level Electrostatic Discharge Analysis (1A6) Jie Xiong, Sam Sagan, Prof. Elyse Rosenbaum Prior State-of-the-Art IC Model for ESD Simulation IC’s external pins are vulnerable to IEC 61000-4-2 ESD and cable discharge events. Signal trace may include TVS, common-mode filter, capacitor → system-specific PDN-aware model Inputs (“features”) are IIO, TPW, L1, C1, C2, R1 Output is VIO V = f(I) is less efficient for circuit simulation but more easily models negative differential resistance Kernel regression is used to learn the model Spline approximation is applied to improve the model efficiency, and the model is extrapolated linearly to higher current levels Nadaraya–Watson kernel regression IC with high component-level ESD reliability may perform poorly at the system-level. Now: approximate the non-parametric I-V model with a parametric model Multi-port model Independent of PDN Currents at supply pins (e.g., VDDIO, VSS) are model features Supply pin response to current pulse at IO Choosing a TVS with lower VON (left) or inserting series resistance (right)—if data-rate permits it—may fix an unreliable design. Generative Models of Air Discharges and Soft Failures* Use circuit simulation to select the right mix of parts! P(system soft-failure) = f (waveform features) Waveform features = g (pre-charge voltage, approach speed, trigger height, properties of EUT) Concept and all figures taken from JEDEC publication 161 IC signal pin model = pulsed I-V curve Critique: Neglects the effect of the board PDN on the I-V curve. Our work: PDN-aware one-port I-V models and multi-port I-V models (examples plotted below) Critique: Static model neglects finite turn-on time of on-board and on-chip protection devices; simulation may not identify failures induced by the initial, high electric field. Our work: Transient model of IC signal pin (poster #2) Modeling: Prior Art and Our Work f and g are probability density functions Developed automated tester for training data collection Naïve Bayes regression used to derive the joint pdf. Example marginal distributions are shown with histogram of samples. Precharge (kV) Approach Speed (mm/s) RMSE 3 27.5 0.028 8 0.016 10 40 0.015 12 0.013 IO pin pulse response by Spectre simulation (PDN aware model is implemented in Verilog A) PDN-aware I-V model verification Model successfully validated against previously unseen data. *Other contributors: Y. Xiu, A. Battini, X. Ma