Chap. 3 Logic Gates and Boolean Algebra Logic Gates : the basic elements of logic circuits(AND, OR, NOT,...) Boolean Algebra A tool for the analysis and design of digital systems Describes relationship between logic circuit’s inputs and outputs Used to help simplify a logic circuit Tab. 3-1 Fig. 3-1 3-1 Boolean constants and variables Only two possible values(Many different terms used synonymously) Logic level 0 and 1 do not present actual numbers but instead represent the state of a voltage variable 3-2 Truth tables Describing how a logic circuit’s output depends on the logic level of circuit’s input(2N possible inputs) Fig. 3-1 Truth Table(2, 3, 4 inputs) A B ? x (a) (c) (b)

3-3 OR Operation with OR gates Output x is a logic 1 if one or more inputs are 1(Fig. 3-2(a)) Boolean expression : x = A + B x= 1 + 1 = 1, x = 1 + 1 + 1 = 1, x = 1 + 1 + …+ 1 = 1 OR Gate : Fig. 3-2(b) Multiple input OR Gate : Fig. 3-3 Exam. 3-1 : Alarm is activated if temperature or pressure exceed a reference Exam. 3-2 : Determine the OR gate output in Fig. 3-5 Exam. 3-3 : Same time transition in A and B input, Glitch or Spike 3-4 AND Operation with AND gates Output x is 1 only when all inputs are 1 Boolean expression : x = AB = A•B OR Gate : Fig. 3-7(b) Multiple input OR Gate : Fig. 3-8 Exam. 3-4, 3-5A, 3-5B X= A+B X= A+B+C A B A B C Fig. 3-2 Truth Table and Symbol Fig. 3-3 Three-input OR X= AB X= ABC A B A B C Fig. 3-7 Truth Table and Symbol Fig. 3-8 Three-input AND

3-6 Describing Logic Circuits Algebraically 3-5 NOT Operation Single input operation, Complement of input NOT operation : x= A NOT circuit : Inverter(Fig. 3-11(b)) 3-6 Describing Logic Circuits Algebraically Boolean logic can describe any logic circuit by Boolean expression. Order of precedence : Parentheses, NOT, AND, OR Fig. 3-12, 13, 14, 15 3-7 Evaluating Logic Circuit Output Given a Boolean expression Evaluate output for given inputs Exam. : Fig. 3-15(a) A=0, B=1, C=1, D=1 Exam. : Fig. 3-15(b) A=0, B=0, C=1, D=1, E=1 1 A 1 x X= A A Fig. 3-11 Truth Table, Symbol, waveform

3-8 Implementing circuits from Boolean expression Evaluation rule for Boolean expression 1) Perform all inversions of single terms 2) Perform all operations within parentheses 3) Perform an AND operation before an OR operation 4) If an expression has a bar over it, perform the expression first and then invert the result Determining output level from a diagram The output can be determined directly from the circuit diagram without using Boolean expression. 3-8 Implementing circuits from Boolean expression Circuit can be implemented from expression 1 1 1 1 1 1 Fig. 3-16 Determining the output from a diagram Fig. 3-17 Constructing a logic circuit from a Boolean expression

3-9 NOR gates and NAND gates Exam. 3-8, 3-9 NAND gate : Exam. 3-10, 3-11, 3-12 3-10 Boolean Theorems Single variable theorems(Fig. 3-25) x • 0 = 0, x • 1 = x, x • x = x, x • x = 0 x + 0 = x, x + 1 = 1, x + x = x, x + x = 1 Multivariable theorems x + y = y + x, x.y = y.x x + (y + z) = (x + y)+ z = x + y + z, x (yz) = (xy)z = xyz, x (y + z) = xy + xz, (w + x)(y + z) = wy + xy + wz + xz x + xy = x : P.81 case 1,2,3,4 or x + xy = x(1+y) = x•1= x x + x y= x = y : (x + x)•(x + y) = 1 •(x + y) = x + y Exam. 3-13, 3-14, 3-15 Fig. 3-19 NOR Gate Fig. 3-22 NAND Gate Commutative laws Associative laws Distributive laws

  3-11 DeMorgan’s Theorems DeMorgan’s Theorems Exam. Exam. Exam. Fig. 3-26, 27 Equivalent circuits implied by DeMorgans Theorems Exam. Exam. Exam. Exam. 3-16 Exam. 3-17 : Determine the output expression and simplify it using DeMorgan Theorems

      3-12 Universality of NAND and NOR gates Implement any logic expression using only NAND or NOR gates Exam. 3-18 : A conveyer belt will shut down whenever specific conditions occur(x = AB + CD) 74LS00 NAND, 74LS08 AND, 74LS32 OR gate 사용(Fig. 3-31)       Fig. 3-29, 30 NAND/NOR gates can be used to implement any Boolean operation Fig. 3-32 Possible implementation

     3-13 Alternate Logic-Gate Representations Standard Logic Symbols : AND, OR, Inverter, NAND, NOR Alternate Logic Symbols : Fig. 3-33 1) Add bubbles on input and output lines that do not have bubbles, and Remove bubbles that are already there 2) Change the operation symbol from AND to OR, or from OR to AND(Inverter is not changed) Note:  The equivalence can be extended to gates with any number of inputs None of the standard symbols have bubbles on their inputs, but all the alternate symbols have bubbles on their inputs The standard and alternate symbols for each gate represent the same physical circuit(No differences) NAND and NOR gates are inverting gates(both the standard and the alternate symbols have a bubble on either the input or the output) AND and OR gates are non-inverting gates(the alternate symbols have bubbles on both inputs and outputs)     Fig. 3-33 Standard and alternate symbols

3-14 Which Gate Representation to Use Logic Symbol Interpretation Active-HIGH : An input or output line has no bubbles Active-LOW : An input or output line does have bubbles Exam. 3-19 : Give the interpretation of the two OR gate symbols 3-14 Which Gate Representation to Use Proper use of the alternate gate can make the circuit operation much clear Active-HIGH Active-HIGH Active-LOW Active-LOW Output goes LOW only when all inputs are HIGH Output goes HIGH only when any inputs are LOW Fig. 3-34 Interpretation of the two NAND gates Output goes HIGH only when any inputs are HIGH Output goes LOW only when all inputs are LOW Fig. 3-35 Interpretation of the two OR gates Active-HIGH Active-LOW Output goes HIGH whenever either A=B=1 or C=D=1 Output goes LOW only when A or B=0 and C or D=0 Original Circuit Fig. 3-36 Alternate Representation

Which Circuit Diagram Should be Used? The answer to this question depends on the particular function being performed by the circuit output If the circuit is used to turn on/off an LED, Relay, or Motor Active-HIGH : On when output goes to 1 Active-LOW : On when output goes to 0 Bubble Placement Whenever possible, choose gate symbols Bubble outputs connected to bubble inputs(Fig. 3-36 (b)) Non-bubble outputs connected to non-bubble inputs(Fig. 3-36 (c)) Exam. 3-20, 21, 22, 23 Asserted Levels Asserted = Active Unasserted = Inactive Labeling Active-LOW Logic Signals Over-bar = Active Low Signal Labeling Bi-state Signals Output signals have two active states Address Decode 회로