Manufacturing Testing

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Presentation transcript:

Manufacturing Testing

Manufacturing Testing What is testing? Apply the input stimuli, test vector, to DUT Observe the response from DUT, and compare with expected results How? Fast and exact Automation

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Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults Transistor faults Bushnell & Agrawal (KAP)

Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments Bushnell & Agrawal (KAP)

Some Real Defects in Chips Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) Time-dependent failures Dielectric breakdown Electromigration Packaging failures Contact degradation Seal leaks Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. Bushnell & Agrawal (KAP)

Occurrence frequency (%) Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 8 5 Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. Bushnell & Agrawal (KAP)

Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4.4 (p. 60-70) of the book. Bushnell & Agrawal (KAP)

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Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value c j 0(1) s-a-0 a d 1(0) g 1 h z i 1 b e 1 k f Test vector for h s-a-0 fault Bushnell & Agrawal (KAP)

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Scan Flip-Flop (SFF) D Master latch Slave latch TC Q MUX Q SD CK Logic overhead MUX Q SD CK D flip-flop Master open CK Slave open t Normal mode, D selected Scan mode, SD selected TC t Bushnell & Agrawal (KAP)

Arbitrary Synchronous Sequencial Circuits Combinational logic PI PO FF Not shown: CK or MCK/SCK feed all SFFs. Bushnell & Agrawal (KAP)

Adding Scan Structure Combinational logic PI PO SFF SCANOUT TC SCANIN Not shown: CK or MCK/SCK feed all SFFs. SCANIN Bushnell & Agrawal (KAP)

Comb. Test Vectors I1 I2 O1 O2 PI PO Combinational logic SCANIN TC SCANOUT S1 S2 N1 N2 Next state Present state Bushnell & Agrawal (KAP)