THUMB INSTRUCTION SET.

Slides:

Advertisements

Similar presentations

ARM versions ARM architecture has been extended over several versions.

Advertisements

Chapter 1. Basic Structure of Computers

THUMB Instructions: Branching and Data Processing

CONDITION CODE AND ARITHMETIC OPERATIONS – Microprocessor Asst. Prof. Dr. Choopan Rattanapoka and Asst. Prof. Dr. Suphot Chunwiphat.

Lecture 5: Decision and Control CS 2011 Fall 2014, Dr. Rozier.

Introduction To The ARM Microprocessor

ARM programmer’s model and assembler Embedded Systems Programming.

Topics covered: ARM Instruction Set Architecture CSE 243: Introduction to Computer Architecture and Hardware/Software Interface.

ARM 7 Datapath. Has “BIGEND” input bit, which defines whether the memory is big or little endian Modes: ARM7 supports six modes of operation: (1) User.

Mainframe Architecture - Evolution Overview  360 Architecture bit GP regs - 8 FP regs at 32 bits or 4 FP regs at 64 bits - 24 bit real addressing.

Computer Architecture

Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz.

ARM Instructions I Prof. Taeweon Suh Computer Science Education Korea University.

The ARM Programmer’s Model

Embedded System Design Center Sai Kumar Devulapalli ARM7TDMI Microprocessor Thumb Instruction Set.

Memory and Addressing How and Where Information is Stored.

CSC 3210 Computer Organization and Programming Chapter 8 MACHINE INSTRUCTIONS D.M. Rasanjalee Himali.

ARM for Wireless Applications ARM11 Microarchitecture On the ARMv6 Connie Wang.

Instruction Set Architecture The portion of the machine visible to the programmer Issues: Internal storage model Addressing modes Operations Operands Encoding.

ARM Processor Architecture (I) Speaker: Lung-Hao Chang 張龍豪 Advisor: Porf. Andy Wu 吳安宇教授 Graduate Institute of Electronics Engineering, National Taiwan.

Chapter 2 — Instructions: Language of the Computer — 1 Memory Operands Main memory used for composite data – Arrays, structures, dynamic data To apply.

©2000 Addison Wesley Little- and big-endian memory organizations.

1 TM 1 Embedded Systems Lab./Honam University r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp)

CS Computer Organization Numbers and Instructions Dr. Stephen P. Carl.

ARM7 Architecture What We Have Learned up to Now.

Instruction Set Architectures Early trend was to add more and more instructions to new CPUs to do elaborate operations –VAX architecture had an instruction.

Ch 5. ARM Instruction Set  Data Type: ARM processors supports six data types  8-bit signed and unsigned bytes  16-bit signed and unsigned half-words.

Lecture 6: Decision and Control CS 2011 Spring 2016, Dr. Rozier.

Addressing Modes in Microprocessors

Immediate Addressing Mode

Control Unit Lecture 6.

CPU Organisation & Operation

ARM Registers Register – internal CPU hardware device that stores binary data; can be accessed much more rapidly than a location in RAM ARM has.

ECE 3430 – Intro to Microcomputer Systems

Assembly Language Assembly Language

Morgan Kaufmann Publishers

The Cortex-M3/m4 Embedded Systems: Cortex-M3/M4 Instruction Sets

Processor Instructions set. Learning Objectives

Chapter 4 Addressing modes

William Stallings Computer Organization and Architecture 8th Edition

Processor Organization and Architecture

Appendix A Classifying Instruction Set Architecture

CSCI206 - Computer Organization & Programming

Architecture CH006.

Computer Architecture & Operations I

MIPS Processor.

Topic 5: Processor Architecture Implementation Methodology

Instruction encoding We’ve already seen some important aspects of processor design. A datapath contains an ALU, registers and memory. Programmers and compilers.

Figure 4- 1: Flowchart for Example 4-3

Architecture Overview

Topic 5: Processor Architecture

Figure 2- 1: ARM Registers Data Size

Branch instructions We’ll implement branch instructions for the eight different conditions shown here. Bits 11-9 of the opcode field will indicate the.

Thumb accessible registers

Instruction encoding We’ve already seen some important aspects of processor design. A datapath contains an ALU, registers and memory. Programmers and compilers.

Control units In the last lecture, we introduced the basic structure of a control unit, and translated our assembly instructions into a binary representation.

The ARM Instruction Set

Branching instructions

ARM Introduction.

Overheads for Computers as Components 2nd ed.

Lecture 11 Z80 Instruction Hong DGU.

Review: The whole processor

Computer Architecture

Instruction Set Summary

Multiply Instructions

CS501 Advanced Computer Architecture

Immediate data Immediate operands : ADD r3, r3, #1 valid ADD r3, #1,#2 invalid ADD #3, r1,r2 invalid ADD r3, r2, #&FF ( to represent hexadecimal immediate.

Instruction execution and ALU

Computer Architecture Assembly Language

MICROCONTROLLERS AND EMBEDDED SYSTEMS Unit – 4 : ARM / Thumb Instruction set GEC

Presentation transcript:

THUMB INSTRUCTION SET

Objectives To understand 16-bit Thumb state operation of ARM Processor. To understand the features of Thumb state operation and how Thumb instructions decompress to ARM Mode. To know the technique of switching between ARM and Thumb mode of operations. To know the similarities and differences between ARM and Thumb mode of operation To understand exception handling and branching in Thumb mode. To understand operation of data processing instructions and data transfer instructions in Thumb mode.

CPU Instruction Set ARM7TDMI processor has two instruction sets: the standard 32-bit ARM instruction set a 16-bit THUMB instruction set.

Processor Operating States ARM state which executes 32-bit, word-aligned ARM instructions. THUMB state which operates with 16-bit, halfword-aligned THUMB instructions.

Thumb Instruction Set ARM architecture versions v4T and above define a 16-bit instruction set called the Thumb instruction set. The functionality of the Thumb instruction set is a subset of the functionality of the 32-bit ARM instruction set. A processor that is executing Thumb instructions is operating in Thumb state. A processor that is executing ARM instructions is operating in ARM state.

Thumb Instruction Set A processor in ARM state cannot execute Thumb instructions, and a processor in Thumb state cannot execute ARM instructions. You must ensure that the processor never receives instructions of the wrong instruction set for the current state. Each instruction set includes instructions to change processor state. Note: ARM processors always start executing code in ARM state.

Thumb state entry

BX and BLX

Eg T=1 on seeing last bit as 1 and ignore last bit and use remaining bits in BX instruction ADR ARM pseudo-instruction Load a program-relative or register-relative address into a register.

CODE32 instructs the assembler to interpret subsequent instructions as ARM instructions CODE16 instructs the assembler to interpret subsequent instructions as THUMB instructions

Example

Binary Encoding

Thumb Programming Model

Conti. All the data processing instructions that operate with and on the 'Lo' registers update the condition code bits (the S bit is set in the equivalent ARM instruction). The instructions that operate with and on the 'Hi' registers do not change the condition code bits, with the exception of CMP which only changes the condition codes. The instructions that are requiring '1 or 2 Hi regs' must have one or both register operands speciﬁed in the 'Hi' register area. 3, 7 and 8-bit immediate ﬁelds is possible depending upon the instructions. Shift amount for shifting instruction is 5 bit.

The following instructions perform ALU operations on to Lo register pair. All instructions in this group set the CPSR condition codes.

Instructions with high register range only cmp sets CC

load sign-extended byte/halfword

Conditional Branch

Egs