EE216A – Fall 2010 Design of VLSI Circuits and Systems Presentation Template * Gray text provides clarifications for the slide content * Min font size: 20 (text), 18 (figures)

Energy-Efficient FPGA Configurable Logic Block (CLB) Team <no> Name 1 Name 2 Final layout numbers Energy [] pJ VDD [] V Area [] mm2 * Make sure the units are correct, use up to 3 decimal places for your numbers

Design Summary A) Adder topology, B) Circuit Style (e.g. linear/square root CSA, static CMOS) C) WHY: about Area, about Delay, other (e.g. moderate Area, fast, regular design) * Replace bullets with a summary of your design * Note: Delay = max {tp_Cin→Cout, tp_Cin→OutX<Y>}, X={A, B, C, D}, Y={0,1} Aspect ratio AR = max {X/Y, Y/X}, X: width, Y: height Schematic Layout Post-layout Verification Delay = [ ] ns X = [ ] μm, Y = [ ] μm Func: Y/N Energy = [ ] pJ AR = [ ] DRC: Y/N VDD = [ ] V Auto P&R: Y/N LVS: Y/N * Replace “[ ]” with your numbers. Choose either “Y” or “N” for “Y/N” EE216A – Fall 2010

Critical-Path Analysis * Highlight critical path, describe significant features Critical block: 8-bit adder adder Carry-bypass has a 40% shorter delay than ripple carry AdrA[1:0] AdrB[1:0] AdrA[3:2] AdrB[3:2] AdrC[1:0] AdrD[1:0] AdrC[3:2] AdrD[3:2] SAMPLE OutA[0] OutA[1] OutB[0] OutB[1] OutC[0] OutC[1] OutD[0] OutD[1] EE216A – Fall 2010

SAMPLE Design Optimization Gate-level sizing for minimum energy * Highlight 2 most important optimization techniques in the next two slides, replace bullets with significant features of your design Gate-level sizing for minimum energy Description of sizing (and values)… CLKB Ci P0 P1 G0 G1 P6 P7 S7 G6 0.96 1.44 0.48 3.84/ 1.92 T-Gate 0.96/ SAMPLE Propagate Carry instead of Carry to reduce transistor count along Manchester chain NMOS only pass gate as all Carry nodes are pre-charged to VDD at CLK=0 Dynamic logic in Ci inverter and G0:7 AND gates  footless Domino in Manchester chain Generate CO and Sum to incorporate the 4X buffer in signal chain. EE216A – Fall 2010

SAMPLE Design Optimization Energy minimization strategy * You may replace the title with the point that you are making (more effective), use bullets to add information, not fill space Energy minimization strategy Use of CAD tools, if any Energy-Delay tradeoff curve exploration Energy minimization through synthesis and/or PnR tools VDD scaling Delay (ns) Energy (pJ) 2 1 3 65% of energy reduced from voltage scaling Further 25% of energy reduced due to lower supply for non-critical paths SAMPLE EE216A – Fall 2010

SAMPLE Physical Layout Top metal layer Indicate size FA1 FA2 FA3 FA0 * Guidelines provided in red text INPUT BUFFER INPUT BUFFER Top metal layer 1 Y = 38.3 μm X = 33.0 μm Indicate size 3 M5 FA1 FA2 FA3 SAMPLE FA0 Highlight critical path 2 OUTPUT BUFFER OUTPUT BUFFER 4 CLOCK CHAIN AR OUTPUT BUFFER OUTPUT BUFFER Aspect ratio: 1.16 FA7 FA6 FA5 FA4 (6) 5 Anything else 1467 μm2 Area Density: 85% INPUT BUFFER INPUT BUFFER EE216A – Fall 2010

Discussion Three most important features of your design * Replace the sub-bullets with the discussion about your design Three most important features of your design (e.g. Minimum delay using transistor sizing) (e.g. Highly regular layout design made easy to route) (e.g. Mirror adder for reduced area) Given another chance, 3 things you would do different (e.g. Change topology, because…) (e.g. Optimize only last few stages to save design time) (e.g. Nothing, I nailed it down! ;)) * Exact number of slides = 7 (exclude slide 1 and simply follow directions) * Do not add extra slides: you have plenty of space to show important points EE216A – Fall 2010