IL MOSFET Professor Ahmed Hemani

Slides:



Advertisements
Similar presentations
ECSE-6230 Semiconductor Devices and Models I Lecture 14
Advertisements

EE130/230A Discussion 12 Peng Zheng 1. Velocity Saturation Velocity saturation limits I Dsat in sub-micron MOSFETS Simple model: E sat is the electric.
Physical structure of a n-channel device:
MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.
EE466: VLSI Design Lecture 02 Non Ideal Effects in MOSFETs.
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Lecture 12: MOS Transistor Models Prof. Niknejad.
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.
Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory
VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.
Lecture 11: MOS Transistor
Introduction to VLSI Circuits and Systems, NCUT 2007 Chapter 6 Electrical Characteristic of MOSFETs Introduction to VLSI Circuits and Systems 積體電路概論 賴秉樑.
CMOS Digital Integrated Circuits
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Lecture #16 OUTLINE Diode analysis and applications continued
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory
Outline Introduction – “Is there a limit?”
The metal-oxide field-effect transistor (MOSFET)
Digital Integrated Circuits A Design Perspective
Week 8b OUTLINE Using pn-diodes to isolate transistors in an IC
Chap. 5 Field-effect transistors (FET) Importance for LSI/VLSI –Low fabrication cost –Small size –Low power consumption Applications –Microprocessors –Memories.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Spring 2007EE130 Lecture 36, Slide 1 Lecture #36 ANNOUNCEMENTS Updated information for Term Project was posted on 4/14 Reminder: Coffee Hour today at ~4PM!
EE105 Fall 2007Lecture 16, Slide 1Prof. Liu, UC Berkeley Lecture 16 OUTLINE MOS capacitor (cont’d) – Effect of channel-to-body bias – Small-signal capacitance.
© Digital Integrated Circuits 2nd Devices VLSI Devices  Intuitive understanding of device operation  Fundamental analytic models  Manual Models  Spice.
Lecture 19 OUTLINE The MOSFET: Structure and operation
ECE 431 Digital Circuit Design Chapter 3 MOS Transistor (MOSFET) (slides 2: key Notes) Lecture given by Qiliang Li 1.
Semiconductor Devices III Physics 355. Transistors in CPUs Moore’s Law (1965): the number of components in an integrated circuit will double every year;
Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.
EE130/230A Discussion 11 Peng Zheng.
EE 466: VLSI Design Lecture 03.
Lecture 2 Chapter 2 MOS Transistors. Voltage along the channel V(y) = the voltage at a distance y along the channel V(y) is constrained by the following.
Qualitative Discussion of MOS Transistors. Big Picture ES220 (Electric Circuits) – R, L, C, transformer, op-amp ES230 (Electronics I) – Diodes – BJT –
ECE 342 Electronic Circuits 2. MOS Transistors
MOS Capacitors MOS capacitors are the basic building blocks of CMOS transistors MOS capacitors distill the basic physics of MOS transistors MOS capacitors.
EE213 VLSI Design S Daniels Channel Current = Rate of Flow of Charge I ds = Q/τ sd Derive transit time τ sd τ sd = channel length (L) / carrier velocity.
NOTICES Project proposal due now Format is on schedule page
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Norhayati Soin 06 KEEE 4426 WEEK 7/1 6/02/2006 CHAPTER 2 WEEK 7 CHAPTER 2 MOSFETS I-V CHARACTERISTICS CHAPTER 2.
1 Metal-Oxide-Semicondutor FET (MOSFET) Copyright  2004 by Oxford University Press, Inc. 2 Figure 4.1 Physical structure of the enhancement-type NMOS.
Introduction to FinFet
EXAMPLE 6.1 OBJECTIVE Fp = 0.288 V
Junction Capacitances The n + regions forms a number of planar pn-junctions with the surrounding p-type substrate numbered 1-5 on the diagram. Planar junctions.
EE141 © Digital Integrated Circuits 2nd Devices 1 Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje.
ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid MOS Transistor ECE442: Digital Electronics.
1 Chapter 5. Metal Oxide Silicon Field-Effect Transistors (MOSFETs)
HW (Also, use google scholar to find one or two well cited papers on symmetric models of MOSFET, and quickly study them.)
Structure and Operation of MOS Transistor
VLSI System Design Lect. 2.2 CMOS Transistor Theory2 Engr. Anees ul Husnain ( Department of Electronics.
EE141 © Digital Integrated Circuits 2nd Devices 1 Lecture 5. CMOS Device (cont.) ECE 407/507.
Device models Mohammad Sharifkhani.
HO #3: ELEN Review MOS TransistorsPage 1S. Saha Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended.
Digital Integrated Circuits A Design Perspective
CMOS VLSI Design CMOS Transistor Theory
MOS Transistor Other handouts Project Description Other “assignments”
The MOS Transistor Polysilicon Aluminum. The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons.
EE141 © Digital Integrated Circuits 2nd Devices 1 Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje.
CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES Part 2.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) allow high density and low power dissipation. To reduce system cost and increase portability,
Introduction to CMOS VLSI Design CMOS Transistor Theory
The MOS capacitor. (a) Physical structure of an n+-Si/SiO2/p-Si MOS capacitor, and (b) cross section (c) The energy band diagram under charge neutrality.
EE130/230A Discussion 10 Peng Zheng.
Damu, 2008EGE535 Fall 08, Lecture 21 EGE535 Low Power VLSI Design Lecture #2 MOSFET Basics.
6.3.3 Short Channel Effects When the channel length is small (less than 1m), high field effect must be considered. For Si, a better approximation of field-dependent.
EE141 Chapter 3 VLSI Design The Devices March 28, 2003.
Lecture #15 OUTLINE Diode analysis and applications continued
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Presentation transcript:

IL 2222 - MOSFET Professor Ahmed Hemani Dept. Of ES, School of ICT, KTH Kista Email: hemani@kth.se Website: www.it.kth.se/~hemani

Usually made of Poly Silicon MOS Capacitor, MOSFET MOS: Metal-Oxide-Semiconductor ~1.5nm thick Few oxide molecules Usually made of Poly Silicon Vg Vg gate metal gate SiO2 SiO2 N+ N+ Si body P-body MOS transistor MOS capacitor Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Energy Diagram at Vg= 0

Flat-band Condition and Flat-band Voltage

Fs is neglible in accumulation Surface Accumulation Fs is neglible in accumulation fs : surface potential, band bending Vox: voltage across the oxide Make Vg < Vfb

Surface Depletion ( vg > vfb )

Surface Depletion Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Threshold Condition and Threshold Voltage Threshold (of inversion): ns = Na , or (Ec–Ef)surface= (Ef – Ev)bulk , or  A = B, and C = D Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Threshold Voltage At threshold, Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Threshold Voltage + for P-body, – for N-body

Strong Inversion–Beyond Threshold Vg > Vt

Inversion Layer Charge, Qinv (C/cm2) Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Choice of Vt and Gate Doping Type Vt is generally set at a small positive value So that, at Vg = 0, the transistor does not have an inversion layer and current does not flow between the two N+ regions. Enhancement type device P-body is normally paired with N+-gate to achieve a small positive threshold voltage. N-body is normally paired with P+-gate to achieve a small negative threshold voltage. Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Review : Basic MOS Capacitor Theory Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Review : Basic MOS Capacitor Theory total substrate charge, Qs Review : Basic MOS Capacitor Theory Modern Semiconductor Devices for Integrated Circuits (C. Hu)

MOS CV Characteristics Modern Semiconductor Devices for Integrated Circuits (C. Hu)

MOS CV Characteristics The quasi-static CV is obtained by the application of a slow linear- ramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very sensitive DC ammeter. C is calculated from Ig = C·dVg/dt. This allows sufficient time for Qinv to respond to the slow-changing Vg . Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Equivalent circuit in the depletion and the inversion regimes (b) (c) (d) General case for both depletion and inversion regions. In the depletion regions Vg  Vt Strong inversion Modern Semiconductor Devices for Integrated Circuits (C. Hu) 18

Modern Semiconductor Devices for Integrated Circuits (C. Hu) MOSFET The MOSFET (MOS Field-Effect Transistor) is the building block of Gb memory chips, GHz microprocessors, analog, and RF circuits. MOSFET the following characteristics: small size high speed low power high gain Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Introduction to the MOSFET Basic MOSFET structure and IV characteristics Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Introduction to the MOSFET Two ways of representing a MOSFET: Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Complementary MOSFETs Technology Modern Semiconductor Devices for Integrated Circuits (C. Hu)

CMOS (Complementary MOS) Inverter Modern Semiconductor Devices for Integrated Circuits (C. Hu)

MOSFET Vt and the Body Effect Two capacitors => two charge components Redefine Vt as Modern Semiconductor Devices for Integrated Circuits (C. Hu)

MOSFET Vt and the Body Effect Body effect: Vt is a function of Vsb. When the source-body junction is reverse-biased, Vt increases. Body effect coefficient: a = Cdep/Coxe = 3Toxe / Wdep Body effect slows down circuits? How can it be reduced? Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Retrograde Body Doping Profiles Wdmax for retrograde doping Wdmax for uniform doping Wdep does not vary with Vsb . Retrograde doping is popular because it reduces off-state leakage and allows higher surface mobility. Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Uniform Body Doping When the source/body junction is reverse-biased, there are two quasi-Fermi levels (Efn and Efp) which are separated by qVsb. An NMOSFET reaches threshold of inversion when Ec is close to Efn , not Efp . This requires the band-bending to be 2fB + Vsb , not 2fB. g is the body-effect parameter. Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Channel voltage Vcs (x) x = 0: Vcs = Vs x = L: Vcs = Vd Qinv in MOSFET Qinv = – Coxe(Vgs – Vcs – Vt0 – a (Vsb+Vcs) = – Coxe(Vgs – Vcs – (Vt0 + a Vsb) – a Vcs) = – Coxe(Vgs – mVcs – Vt) m º 1 +a = 1 + 3Toxe/Wdmax m is called the bulk-charge factor Typically m is 1.2 but can be simplified to 1 Modern Semiconductor Devices for Integrated Circuits (C. Hu)

How to Measure the Vt of a MOSFET ? B Method A. Vt is measured by extrapolating the Ids versus Vgs curve to Ids = 0. Method B. The Vg at which Ids =0.1mA W/L Modern Semiconductor Devices for Integrated Circuits (C. Hu)

m is typically 1.2 but can be simplified to 1 Basic MOSFET IV Model Ids= WQinvv= WQinvmnE = WCox(Vgs– mVcs – Vt)mndVcs/dx IdsL = WCoxmn(Vgs – Vt – mVds/2)Vds Process Transconductance Gain factor m is typically 1.2 but can be simplified to 1 Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Vdsat : Drain Saturation Voltage Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Saturation Current and Transconductance Drain current in saturation region Transconductance: gm= dIds/dVgs Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Saturation – Pinch Off Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Channel Length Modulation Increasing the Vds has the effect of the reducing the channel length as the depletion region on the drain side increases. Channel length reduction  lower resistance  Increase in Drain Current More pronounced for short channels One of the five short channel effects

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Velocity Saturation x (V/µm) c = 1.5 u n ( m / s ) sat = 10 5 Constant mobility (slope = µ) Constant velocity sat n v E + = 1 m E << Esat : v = m E n E >> Esat : v = m Esat n Velocity saturation has large and deleterious effect on the Ion of MOSFETS Modern Semiconductor Devices for Integrated Circuits (C. Hu)

MOSFET IV Model with Velocity Saturation Vcs /L– the average electric field is replaced by inv ds v WQ I = sat cs ns t gs oxe ds E dx dV V mV WC I / 1 ) ( + - = m cs sat L V ds t gs ns oxe dV E I mV WC dx ] / ) ( [ - = ò m sat ds t gs ns oxe E V I m WC L / ) 2 ( - = Modern Semiconductor Devices for Integrated Circuits (C. Hu)

MOSFET IV Model with Velocity Saturation ds t gs ns oxe + - = 1 ) 2 ( L E V I channel - long sat ds / 1 + = Modern Semiconductor Devices for Integrated Circuits (C. Hu)

MOSFET IV Model with Velocity Saturation dV dI ds , Solving = L mE V m sat t gs dsat / ) ( 2 1 - + = A simpler and more accurate Vdsat is: L E V m sat t gs dsat 1 + - = 2 v º E dsat sat m ns Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) EXAMPLE: Drain Saturation Voltage Question: At Vgs = 1.8 V, what is the Vdsat of an NFET with Toxe = 3 nm, Vt = 0.25 V, and Wdmax = 45 nm for (a) L =10 mm, (b) L = 1 um, (c) L = 0.1 mm, and (d) L = 0.05 mm? Solution: From Vgs , Vt , and Toxe , mns is 200 cm2V-1s-1. Esat= 2vsat/m ns = 8 104 V/cm m = 1 + 3Toxe/Wdmax = 1.2 1 - | ø ö ç è æ + = L E V m sat t gs dsat Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) EXAMPLE: Drain Saturation Voltage 1 ç è æ + - = L E V m sat t gs dsat | ø ö (a) L = 10 mm, Vdsat= (1/1.3V + 1/80V)-1 = 1.3 V (b) L = 1 mm, Vdsat= (1/1.3V + 1/8V)-1 = 1.1 V (c) L = 0.1 mm, Vdsat= (1/1.3V + 1/.8V)-1 = 0.5 V (d) L = 0.05 mm, Vdsat= (1/1.3V + 1/.4V)-1 = 0.3 V Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Idsat with Velocity Saturation Substituting Vdsat for Vds in Ids equation gives: L mE V I channel - long C mL W sat t gs dsat s ox + = 1 ) ( 2 m Very short channel case: t gs sat V L E - << ) ( L mE V C Wv I sat t gs ox dsat - = ) ( V C Wv I t gs ox sat dsat - = Idsat is proportional to Vgs–Vt rather than (Vgs – Vt)2 , not as sensitive to L Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Current-Voltage Relations A good ol’ transistor 0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT Quadratic Relationship

Velocity Saturation I V The IDSAT in short Channel Device has linear dependence on VGS as opposed to square dependence thus significantly reducing the drain current delivered for a given voltage and thus slows down the device I D V DS DSAT GS - V T = V DD Long-channel device Short-channel device The Short Channel Device enters saturation before VDS > VGS - VT

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Velocity Saturation What is the main difference between the Vg dependence of the long- and short-channel length IV curves? Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Sub-Threshold Conduction 0.5 1 1.5 2 2.5 10 -12 -10 -8 -6 -4 -2 V GS (V) I D (A) VT Linear Exponential Quadratic The Slope Factor S is DVGS for ID2/ID1 =10 Typical values for S: 60 .. 100 mV/decade

A Unified Model Velocity Saturated Linear Saturated G S D B VDS=VDSAT 0.5 1 1.5 2 2.5 x 10 -4 V DS (V) I D (A) Velocity Saturated Linear Saturated VDSAT=VGT VDS=VDSAT VDS=VGT A Unified Model S D G B

Transistor Model for Manual Analysis

The Transistor as a Switch

The Transistor as a Switch

Dynamic Behavior of MOS Transistor

The Gate Capacitance x L Polysilicon gate Top view Gate-bulk overlap d L Polysilicon gate Top view Gate-bulk overlap Source n + Drain W t ox n + Cross section L Gate oxide

Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off

Gate Capacitance Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation

Diffusion Capacitance Channel-stop implant N 1 A Side wall Source W N D Bottom x Side wall j Channel L S Substrate N A

Capacitances in 0.25 mm CMOS process

MOSFET – Some Secondary Effects V T V T Low V threshold Long-channel threshold DS VDS L Threshold as a function of Drain-induced barrier lowering the length (for low V ) (for low L ) DS

Parasitic Resistances Polysilicon gate Drain contact R G D S VGS,eff RS RD L D W Drain RS,D = R LS,D/W + RC

SPICE Models for the MOS Transistor Three Levels Level 1 Long Channel, Channel Length Modulation Level 2 Geometry based that includes detailed device physics Velocity saturation, mobility degradation, DIBL Analytical physics based model makes it complex and inaccurate Level 3 Semi-empirical model Measured data to calibrate and decide the main parameters Accurate and efficient. Widely used.

BSIM3-V3 Parameter Category Description Control Selection of level and models for mobility, capacitance and noise DC Parameters for threshold and current and calculations AC & Capacitance Parameters for capacitance computations dW and dL Derivation of effective channel length and width Process Process parameters such as oxide thickness and doping concentrations TOX, XJ, GAMMA1, NCH, NSUB Temperature Nominal temperature and temperature coefficients for various device parameters TNOM Bin Bounds device dimensions for which the model is valid LMIN, LMAX, WMIN, WMAX Flicker Noise Noise model parameters

SPICE Transistor Parameters Parameter Name Symbol SPICE Name Units Default Value Drawn Length L m - Effective Width W Source Area AREA AS m2 Drain Area AD Source Perimeter PERIM PS Drain Perimeter PD Squares of Source Diffusion NRS 1 Squares of Drain Diffusion NRD