School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Course Tutor Dr R E Hurley Northern Ireland Semiconductor Research Centre School of Electrical & Electronic Engineering The Queens University of Belfast

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland 2. The future of silicon Moores Law What is realistic and possible for tomorrows production (advance to 22nm)? What next? New materials Blue skies and on into the future. Sheets of carbon atoms folded into a cylinder Unusual strength and electrical properties Promise to revolutionise electronics, computers, chemistry and materials science

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland International Technology Roadmap for Semiconductors

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Proposed new technologies Strained Si and SiGe Improve high-k/metal gate further Orientation (110 re 100) Multi-gates III-V or Ge Metallic S/D

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Current question today is how to advance to 22nm? (in production) IBM Research device

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Current situation for immediate future 1.Lithography (immersion, EUV) 2.Mobility enhancement (strain eng) 3.High-k/metal gates improvements 4.Cu plugs contacts 5.Porous low-k interconnects.

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Lithography nm: Water immersion with ArF (NA = 1.35) nm: Double patterning technique nm: EUV expected (critical parameters: feature resolution, line-edge roughness (LER) and exposure sensitivity. )

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Researchers used double patterning with water-based immersion lithography to achieve a proof-of-concept 32 nm flash memory pattern. The final k 1 was 0.19 after the split.

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Strain techniques A buried SiGe island is very effective at inducing uniaxial tensile strain in the nFET channel for a 15% improvement in drive current. The TEM shows the device following silicon regrowth in the source/drain. (Source: IBM) 32 – 45 nm: strain engineering for CMOS. Put the silicon lattice under strain improves mobility in channel. 1.Epitaxial SiGe in source and drain 2.Compressive stressed nitride over gate 3.Strained SOI

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Ge layer on bulk Si Si layer on bulk Ge Ge Si Ge on Si Si on Ge Si Ge Si expands laterally contracts vertically Ge contracts laterally expands vertically

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Strained Silicon SiGe (X% Ge) Silicon wafer Epitaxial Silicon Graded SiGe (0-X% Ge) Strained silicon for high speed devices

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland relaxed Si 1-x Ge x step step Si Relaxed silicon germanium layer by graded growth on silicon N.B. diagram exaggerated. Lattice mismatch is only 4.2%! With CVD, production of layers is relatively easy. At QUB we have experimented up to 60 layers.

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Strained silicon for novel band gap engineered n- and p- MOSFETs with significantly improved performance compared to pure silicon. Strained silicon growth onto silicon germanium

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Cross-sectional TEM image of a virtual substrate grown at 800 °C by ultra-high- vacuum CVD, showing the compositionally graded buffer Si 1x Ge x layer (x from 0 to 0.25) with significant number of dislocations and the constant-composition Si 0.75 Ge 0.25 buffer free from dislocations [Churchill et al., 1997]. TEM image of graded SiGe buffer layer

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Strained silicon MOST n+n+ n+n+

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Intel Approach to Strained Silicon Silicon in channel under compressive stress P MOST 25-50% Silicon in channel under tensile stress n MOST 10%

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Low-k for interconnects At 22nm The interline capacitance between conductor lines (interconnects) must be reduced. Use low-k (2.2 to 2.5)

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Threshold voltage, Vt,variability problem in MOSFETs As size reduces statistical variations in Vt start to show Random dopant fluctuations are major cause For long transistors V t = V FB + 2 Φ F - Q d /C ox [ V FB == flat band voltage, Φ F is Fermi potential, Q d = depletion charge and C ox = MOS structure capacitance.]

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland The Vt fluctuations due to the random variations of dopant in the channel are given by But this model does not work when dimensions are very small i.e. ΔVt is a function of area and dielectric thickness Threshold voltage, Vt,variability problem in MOSFETs

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Space-charge at source/drain junctions is around 0.05 µm for 0.18 and 0.12µm CMOS. When CMOS CD < 0.12µm, space-charge affects channel length significantly and potential barrier is reduced and Vt is reduced. This effect can vary from one transistor to the next. Short channel effect

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland High-k reduced ΔVt, but further improvements needed: Control work-function in the TiN gate 1.nFET – Thin lanthanum oxide layer cap on high-k 2.pFET - Thin aluminium oxide layer on high-k Threshold voltage, Vt,variability problem in MOSFETs

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Copper interconnects into memory devices Flash memory uses high fields needing thicker barrier layers and denser oxides The interconnect of a flash device shows on-pitch Metal 1 with high-aspect-ratio vias above, which press the capabilities of barrier/seed coverage and copper fill. (Source: Micron)

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Copper for contacts 32 nm: Copper to replace tungsten plugs (plugs make contact to S/D). Contact resistance affects RC and power consumption. Issues are barrier layers to protect silicon. (Cu poisons Si!). Barrier must be thin but reliable!

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Beyond 22nm and high risk research Multi-gate devices (MuGFETs) Ge and III-V System on chip and 3D fusion technology. Possible and realistic but difficult

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland MuGFET Benefits from reproducible threshold voltage and low OFF leakage, but difficult to implement in production

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland CMOS Looking beyond 2010, for CMOS new materials required: channelFor channel: SiGe, Ge or III-V high k dielectric metal gatesIn combination with high k dielectric and metal gates (to replace polysilicon) ITRS New material needs

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Historically first bipolars and ICs were made from Ge Si replaced Ge because of SiO 2 properties GeO is unstable at C being volatile Bardeen, Brattain, Shockley, Nobel Prize, 1956 Germanium, early days.

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Importance of germanium in todays technology Ge now reconsidered for: 1. Extending scaling limits of CMOS technology (<45nm) 2. Near IR optical telecommunication devices 3. Solar energy

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK GeSiGaAs Energy gap (ev) Intrinsic carrier conc. n i (cm-3) 2.4 x x ~9 x 10 6 Electron mobility (cm 2 /Vsec) Hole mobility (cm 2 /Vsec) Dielectric constant Breakdown field (v/µ)~8~30~35 Crystal Structurediamond Zinc-blende Lattice Constant (Ǻ) Density, ρ (g/cm 3 ) Melting point ( o C) Thermal conductivity (W/cm o C) ? Thermal Coefficient of Expansion ( o C -1 ) 5.8x x x10 -6 Semiconductor Properties - Ge, Si, GaAs compared.

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Germanium significant properties Electron mobility 3900 cm 2 /Vs (Si 1500) Hole mobility 1900 cm 2 /Vs (Si 450) Band gap 0.66 eV (Si 1.1 eV)

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Ge provides high electron and hole carrier mobility -- faster CMOS, larger drive currents. Compatibility with high k dielectric and low temperature metal gate technology Ge lattice match to GaAs permitting epitaxial growth -- n channel MOSFET Integration of rf & quantum electronics -- integration of opto-electronics (smaller optical band-gap) Advantages of Germanium

3 rd July 2008 Sheffield Germanium Highest hole mobility High electron mobility Low energy band gap High density More fragile than silicon Scarce, expensive Suitable for GaAs epitaxy Applications High performance CMOS Low temperature operation IR detection/imaging High energy particle detection Integrated optics & electronics Solar cells

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Germanium problems with MOST Unstable oxide.Unstable oxide. GeO 2 forms volatile GeO at C, hence poor passivation of Ge surface Dopant solubilityDopant solubility (in electrical terms) is poorer than expected. (Clustering? Vacancy-acceptor centres?) Dopant lossDopant loss during annealing (related to ion- implantation damage) success with BSome success with B, but n dopants ( implant damage greater) require higher anneal temps. Leads to high-k crystallisation, Ge diffusion etc..

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Germanium: More problems! Smaller band-gap surface leakageSmaller band-gap (than Si) leads to high intrinsic (n i ),carrier concentration leading to surface leakage in p-n diode periphery. (problems also with surface states) [Satta, 2006} Lattice mismatch Thermal expansionLattice mismatch with silicon substrate means grading layers of SiGe or smart-cut type solution if it can be made to work. Thermal expansion coefficients are significantly different.

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Houssa et al., from Germanium-Based Technologies, Elsevier Ltd GeMOSFET: p-n junction and metal gate/dielectric stack Volume and surface charge carriers must be considered GeMOSFET schematic

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Thin epi-Si oxidised, with HfO 2 by ALD give C-V improvement over GeON interlayer Houssa et al., 2007 Ge gate-stack issues

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK GeMOSFET – circular geometry Chi On Chui, Stanford University Self-aligned, surface channel p- GeMOSFET ZrO 2 (EOT 6-10 A), Pt gate. BF 2 35keV implant, 400C max temp in entire process.

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK TEM showing interface problems direct onto GeHfO and ZrO direct onto Ge leave a 3A GeO layer- enough to create instabilities and irreproducible characteristics Ge/GEO2/HfO2 gate stack (Houssa et al., 2007) High density interface states, high leakage.

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Channelling is significant End of range straggle Annealing to remove damage and activation leads to loss of dopant. Annealing temp must be kept below 400 to 500C to prevent: 1. Crystallisation of high-k material. 2.Out-diffusion of dopants. 3.Degradation of interfaces. Shallow junctions: ion implantation problems

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Good p-channel devices OK n-channel mobility is poor Therefore, Ge for p-MOS GaAs or strained Si for n-MOS GaAs can be grown by epitaxy on Ge Can GeOI really be used for CMOS?

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Germanium on Insulator (GeOI) Other possibilities for GeO Enhanced performance devices High speed photodetectors Template for GaAs epitaxy (Si/III-V integration)

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK Smart-Cut method for GOI (QUB)

School of Electronic Engineering and Computer Science Queens University Belfast, N.Ireland, UK

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland 3D integration fusion technology SEM of a 3-D via chain with 10,000 vias/mm 2 density after etching the silicon in the top die. (Source: IMEC) FUSION = integration of memory, logic, sensor, processor and software using 3D stacked ICs

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Optoelectronics: Photons weigh 250,000 times less than electrons, so why not use them to carry data? Bringing optical technology down to the processor level, DNA: ?? Immersion lithography: This technique entails putting wafer in water and shooting the picture! Imprint lithography: A stamp (by e-beam litho) is immersed in liquid to create a pattern. HP. EUV lithography: By using highly polished mirrors and a laser EUV machines can create lines a few nanometers in length. Intel, AMD and IBM are the big proponents. 2009? (Think not! SemiconInt)

School of Electrical and Electronic Engineering Queens University Belfast, N.Ireland Spintronics: Uses the magnetic field created by an electron's spin (rather than the transport of electrons). Phase change: memory technology that relies on heating, and reheating, CD-like material. Philips and Intel, Nanowires and nanotubes: transport electrons from one point to another to create a 1 or 0. how to put billions into arrays.? Crossbar latches: This is one of the more radical transistor makeovers, HP. bad circuits no statistical consequence Resistance switching: Resistance change of molecule. III-V compounds: These materials behave like silicon but are faster. They also cost a lot more.