1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory Management and Protection Part 3:Virtual memory, mode switching, example dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

1/1/ / faculty of Electrical Engineering eindhoven university of technology Virtual memory (1) The logically addressable memory size can exceed the physical memory size –Common situation with multiple linear memory spaces No problem if the actually used amount of memory fits in physical memory –Rely on address translation to 'pack' the memory

1/1/ / faculty of Electrical Engineering eindhoven university of technology Virtual memory (2) Memory in use > physical memory: problem –Hold part of used memory in physical memory –Store remainder somewhere else, f.i. on a hard disk Keep this invisible to processor: 'virtual memory' –Hardware stops invalid memory access –Starts routine to move data into physical memory –Then re-tries the failed memory access which may be in the middle of an instruction!

1/1/ / faculty of Electrical Engineering eindhoven university of technology The 'program locality principle' Consecutive accesses are generally not far apart –The 'working set' contains the active memory areas –Run at full speed if these are kept in real memory! last instruction address (x) p (x+1) last stack access (y) p (y+1: POP)(y-1: PUSH) last data access (z) p (z+1: Arrays, Strings) mean stack frame size

1/1/ / faculty of Electrical Engineering eindhoven university of technology Virtual memory hardware support bits These work for pages as well as segments Present bit: in memory if set, otherwise on disk –Processor aborts access if this bit is reset Accessed bit: set on each read or write access –Detect activity for determining the working set Written bit: set on each write access –No need to write back to disk if unchanged

1/1/ / faculty of Electrical Engineering eindhoven university of technology A A A A A The working set - clock algorithm (1) 'swap in' A acces s A A P=1 P=0 'swap out' I need you !

1/1/ / faculty of Electrical Engineering eindhoven university of technology The working set - clock algorithm (2) Swap out writes only if Written bit set Swap in sets Accessed and Present, resets W This algorithm is often used (works very well) –Working set pages/segments set A bit a lot they are not swapped out! –Fair swap out decisions, even under high system load –Will always find something to swap out (robust)

1/1/ / faculty of Electrical Engineering eindhoven university of technology 16 K paged memory, 1 K pages 0 16 The fragmentation problem 16 K segmented memory K 2 K 2.5 K 4 K 1.5 K 4.5 K 3.5 K 1.5 K 3.5 K Unusable space inside pages !! 6 K free, but does not fit !! Memory is fragmented outside segments: external fragmentation Memory is fragmented inside pages: internal fragmentation

1/1/ / faculty of Electrical Engineering eindhoven university of technology Pages versus segments Fixed-size pages ease swapping to/from disk Segments provide more complete protection Intel uses segmenting AND paging –Protection based upon the segments (done first) –Virtual memory based upon paging (done last) –Two translation steps needed The P, A and W bits are offered in hardware, managing virtual memory is done in software!

1/1/ / faculty of Electrical Engineering eindhoven university of technology Switching from user to system mode (1) Generally done with a kind of software 'interrupt' –Hardware interrupt routines run in system mode too –They need the same mode switching logic but interrupts remain enabled here Interrupt routine start addresses in protected table –Not possible to enter system mode at arbitrary address –Called routine is responsible for checking parameters

1/1/ / faculty of Electrical Engineering eindhoven university of technology Switching from user to system mode (2) The number of software interrupts is limited –Signetics and Zilog Z8000: ONE 'service call' Other methods exist for protected switching –DEC Alpha: protected library of subroutines –Intel 80286: pseudo segments called call gates

1/1/ / faculty of Electrical Engineering eindhoven university of technology User applications: PL 3 Intel protection example –Code access:only in same level or higher levels –Data access:only in same level or lower levels –Stack access:only in same level (separate stacks!) Device drivers: PL 2O.S. core: PL 1 Kernel: PL 0 PL: Privilege Level

1/1/ / faculty of Electrical Engineering eindhoven university of technology 16 bits Intel segment selector Global table with 8192 shared segments Task-local table with 8192 private segments 'Requested Privilege Level' allows lowering the protection level of a segment (towards PL 3) 'RPL 2 bits local/global 1 bit segment number 13 bits

1/1/ / faculty of Electrical Engineering eindhoven university of technology 64 bits Intel memory segment descriptor –CODEreadable, 'conforming' (for libraries) –DATAwritable, stack (reverses limit checking) –TASK STATE(registers, 4 stack pointers, active segs.) –LOCAL TABLE(only in global segment table) limit 16 bits base 24 bits Present 1 bit Accessed 1 bit 'PL 2 bits Type & access rights Location Size Virtual memory No Written bit !

1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel calls and jumps Within same segment only needs offset Other segment at same PL needs offset & selector To higher protected code (lower PL) uses 'call gate –These are stored in segment tables (pseudo- segment) –CALL instruction points to this pseudo-segment but the offset in instruction is overruled by call gate –Data copied automatically between stacks 'PL 2 bits Present 1 bit offset 16 bits code segment selector stack copy block size

1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel traps and interrupts Use 256 entry 'interrupt descriptor table –Which contains trap gates and interrupt gates –These are call gates without stack data copying –An interrupt gate disables interrupts automatically 'PL 2 bits Present 1 bit offset 16 bits code segment selector

1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel I/O protection Global 'I/O Privilege Level' indicates the highest PL value at which ANY I/O is allowed –Higher PL level code traps on IN & OUT instructions Each task has a bitmap in the task state segment –Each bit corresponds with an I/O port –Accessing I/O port with bit at 0 generates trap –Size of bitmap variable, undefined ports always trap

1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel multitasking support 'Task state' segments store task information –Special register points to active task state segment Task switch with JUMP through a 'task gate' 'PL 2 bits Present 1 bit task state segment selector 1)Save register set in active task state segment 2)Get address of new task state and declare it active 3)Load register set from this segment, including PC 4)Restart program execution for the new task PL 0 only: kernel !