A new Interlock Design for the TESLA RF System H. Leich1, A. Kretzschmann1, S. Choroba2, T. Grevsmühl2, N. Heidbrook2, J. Kahl2, 1(DESY Zeuthen) 2(DESY Hamburg) The Problem The Interlock Architecture Implementation Status of the Project 4/28/2019 Holger Leich, DESY Zeuthen

Main Task of the Interlock Sytem --> to prevent any damage from the cost expensive components of the RF station --> also to prevent any damage from other environment Sources of Interlock Error Signals hard component failures (non-reversible hardware malfunction) --> broken cable or damaged contact, dead sensor, ... soft errors (e.g. sparks in the klystron or wave guide system, temperature above a threshold, ...) error conditions caused by transient noise from the RF station itself 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen PITZ Interlock Subsystems Control system Clear, Clock, Dout Klystron interlock Din safety & person IL o.k. RF- leak 1&2 Person interlock enable Klystron 1&2 Low level RF 12 gun signals separate Clock... all input signals internal states output signals masks to BIS all input signals internal states output signals enable magnets 1 & 2 laser pulse length laser rep. Rate enable RF enable alig.laser enable BIS 1&2 enable shutter1 1&2 enable RF Magnets Beam inhibit system Laser interlock Gun IL o.k. reset gun interlock solenoid supply o.k. laser shutter PM Gun fast Gun interlock ADCs 9 analog signals Profibus 4/28/2019 Holger Leich, DESY Zeuthen

Architecture of the existing Interlock Strictly digital hierarchical Interlock Process Analysis Output to Process Analog Process Input Digital Process Input Analog Output Digital Output Adapter Unit Adapter Unit Sensor Sensor Klystron, RF Station 4/28/2019 Holger Leich, DESY Zeuthen

Klystron Interlock Inputs Digital Inputs - Oil levels - Cooling water flow - Vacuum pump current Analog Inputs - Oil temperature - Cooling water temperature - Heater current - Solenoid current - SF6 gas pressure 4/28/2019 Holger Leich, DESY Zeuthen

Klystron Interlock Inputs / Outputs Preprocessed Inputs - Person interlock o.k - RF leakage detector - Modulator ready - Gun interlock o.k. - RF system ready Interlock Outputs - Modulator on - Heater power supply on - Solenoid power supply on - RF enable 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen Response Times Ultra Fast (UF): Rt < 1 µs Fast (F): Rt = 1 ... 5 µs Slow (SL): Rt > 5 µs --> Actual implementation only SL and F --> ca. 40 signals to process 4/28/2019 Holger Leich, DESY Zeuthen

Overview over the new Interlock Design Master Control System Component Characteristics Predefined Curve Data Measured Characteristic Interlock Logic implemented based on a Microcontroller (Processor Core) User programmable ASIC (FPGA) Time discrete digital data Analog/Digital Process Output Digital Process Input Analog Process Input Sensor Sensor Adapter Unit Klystron, RF Station 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen The Implementation Implementation Constraints limited space in TESLA-tunnel combine Control & Interlock Functions into only one crate per RF-station perform communication between modules via backplane ( no extra cable for communication) process-I/O with no cables to the front side of the crate; all cables from rear site use a standard with stable, fast enough & easy to implement bus interface use a standard that gives flexibility at the level of system integration ( definition of backplane-ressources : standard bus, user defined bus, …) use a standard that saves investment over longer time scale use a standard to have the option to buy commercial available products (CPU`s, DAQ components, piggy pack, e.g. IP modules, ...) use a standard that offers the option of additional boardspace (rear transition option) Other, DESY defined constraints 4/28/2019 Holger Leich, DESY Zeuthen

Implementation Details DESY decision: Use a VME64x system - VME64x introduces 5 row (160 pins) connectors J1/J2 and an optional 95pin-connector J0 415 pins Total = 210 pins VME System + 205 pins User Defined => enough pin resources per slot and per backplane to build a compact interlock/control system VME is a stable, fast enough and easy to implement bus and instrumentation system mixed use of VME and VME64x devices possible rear transition board option easy system integration DESY: 205 pins User Defined: 64 pins per slot used for rear transition 141 pins across the backplane to implement a fast user bus 4/28/2019 Holger Leich, DESY Zeuthen

DESY-VME64x-Backplane J1 J0 J2 ( slot-pin configuration ) 4/28/2019 z a b c d J1 32 1 e d c b a J0 19 1 z a b c d J2 per Slot per Slot 32 141 pin User Defined Bus (GTL) Rear I/O Connections: 64 pins VME64x Standard 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen Interlock / Control Crate VME-CPU (VME-Controller) Interlock Master / Sequencer Up to 16 I/O-Modules Profibus HD Reserve Control- / Monitoring Interlock 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen Interlock / Control Crate (Side view) J1 J2 J0 Front Boards (160 mm) VMEbus Interface Interlock / Master Logic I/O resources User Bus Interface Rear Boards (160 mm) Rear Transition Signals Additional I/O-functions Signal conditioning VME64x Backplane, 160pin-J1/J2, 95pin-J0 (with J0 full & J2-pins rows z,d bussed) 4/28/2019 Holger Leich, DESY Zeuthen

Structure of the DESY User Defined Bus Sytem Master / Sequencer 110 lines connected: 22 Time-Mux-Bus 34 Control-Bus 16 Event-Bus 2 BusInit, BusClock 4 Reserve BusControl 32 Reserve (bi-directional) (all lines GTL) BusInit, BusClock I/O-Module & other Modules Time-Multiplex-Bus Control-Bus Event-Bus Reserve 31 lines spare at backplane for free use by other (future) components / systems Event-Bus and/or Reserve could be defined as “LAM” (Emergency Line) for Interlock Signals with very high priority 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen Bus Timing Time Mux Bus BCLK Init_l ADDR 1 2 3 Data D(0) D(0) D(1) D(2) D(3) Control Bus BCLK STRB_l WE_l Address ADDRi ADDRj Data Data Out Data In Event Bus BCLK SRVRQ_l 4/28/2019 Holger Leich, DESY Zeuthen

Architecture of the Interlock Master / Sequencer ACEX EP1K100 FC484 AM[5..0], AS, DS[1..0], Write, LWord, Iack, IackIn VME Access Control VME Interrupt Control `ABT2244 Dtack, Berr, IRQ[7..4], IackOut Req Ack Req Ack Ack `F38 ROM Access Arbiter & Address Mux Req Ctrl Out Ctrl In `ABT162244 Data Bus DB[15..0] Data Bus Interlock I/O Boards VME Bus ROM 512 x 16 Interlock Logic (Sequencer/ Controller) Address Bus A[23..1] Address Bus Ack `ABT2244 DPM Access Control Req Data Out Data In Data Mux CS CE WE Address Mux Nonvolatile SRAM 64K x 16 (4 x U634H256CSK25) 4/28/2019 Holger Leich, DESY Zeuthen

Other Modules under Construction Digital Input Module Digital Output normal Digital Output ultrafast Analog IO fast Digital IO LWL (Rear Module) 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen Status of the Project Architecture definition  finished Backplane design & manufacturing  finished Master/Sequencer design  finished/assembled/tested I/O Module design  DigiIn: assembled, not yet tested DigiOut, DigiOutFast: layout process Analog I/O: design not yet finished Digital IO LWL: not yet designed Firmware design  ongoing 4/28/2019 Holger Leich, DESY Zeuthen

Existing RF Interlock System 4/28/2019 Holger Leich, DESY Zeuthen

Holger Leich, DESY Zeuthen VME64x-Crate with DESY VME64x Backplane 4/28/2019 Holger Leich, DESY Zeuthen

Interlock Master / Sequencer Module 4/28/2019 Holger Leich, DESY Zeuthen