Muon Port Card Latency, October 2015 Old Virtex-E mezzanine New Spartan-6 mezzanine Data path, from the peripheral backplane input to TLK2501 serializers (three old links) ~90 ns Serialization in TLK2501 at 80MHz (three old links) ~24 ns Data path, from the peripheral backplane input to Spartan-6 GTP serializers (8 new links) - ~96 ns Serialization in Spartan-6 GTP transmitters at 160MHz, (8 new links), TX buffer disabled for low latency; based on Xilinx documentation ~41 ns

Trigger Path Latency; Measurements of 2005 110 ns (MPC) + 500 ns (fiber) + 50 ns (DESER)

MTF7 Based Muon Sorter, October 2015 Rx and Tx buffers enabled in the GTH blocks Serialization and deserialization at 250Mhz (10Gbps) No processing of any kind in the FPGA Latency of GTH Tx + GTH Rx = 170ns – 70ns (14 m fiber) = 100ns 170 ns