A new family of pixel detectors for high frame rate X-ray applications Roberto Dinapoli†, Anna Bergamaschi, Beat Henrich, Roland Horisberger, Ian Johnson, Philipp Kraft, Aldo Mozzanica, Bernd Schmitt, Xintian Shi, Dominic Suter The chip The pixel* Technological process UMC 0.25 µm Power supplies 1.1 V (analog), 2V (digital), 1.8V (I/O) Radiation tolerance Radiation hard design (>4Mrad) Pixel array 256 x 256 = 65536 Chip size 19.3 x 20 mm2 Other features Overflow control, XY-addressability and analog out for testing Pixel size 75 x 75 µm2 Gain 44.6 μV/e- Peaking time 31 ns Ret. to zero @ 1% 151 ns Noise (simulated) 135 e-rms Static power dissipation 8.8 μW/pixel Transistor count 430/pixel Pixel counter 12 bits, binary, double buffered for continuous readout, configurable (4,8,12 bit mode) Threshold adjust. 6 bit DAC/pixel At the Swiss Light Source (SLS) we are developing a new family of hybrid, single photon counting detectors for high frame rate X-ray applications. Systems up to 9 Mpixel (~550 cm2) will be built, targeting mainly protein crystallography, small angle scattering and coherent diffraction imaging. The readout chip was received from fabrication the third week of May and is at present being integrated in the test setup. The chip is designed with Hardening By Design techniques (HBD: enclosed layout transistors, p-guard rings) to obtain high radiation tolerance from a standard commercial CMOS technology. The new readout chip keeps the noise and speed performance of the previous chip of the Pilatus family (Pilatus II) and improves it in every other respect; in particular pixel size (reduced >5x), pixel count (>11x), double buffering, but most of all readout speed (>1000x for big detectors). Picture of a “single”, a pixel silicon sensor prototype which will be bonded to a single chip, close to a Pilatus II (PII) sensor. The smaller pixel size and bump bonding pitch are evident in the microscopy picture in the inset. ~2 cm ~2 cm *Simulations done with “standard” settings. “Low noise” or “high speed” settings can improve performance for applications with specific needs. New sensor PII sensor

Chip readout scheme Frame rate Mode of operation Max. frame rate (100MHz DDR clock) Maximum counting rate 4 bits 24 kHz 380kHz/pix* 8 bits 12 kHz ~1MHz/pix** 12 bits 8 kHz *Limited by counter depth ** Limited by analog frontend speed The readout architecture is targeting very fast frame rates. For this reason a high level of parallelism is embedded in the chip. A full row of pixel counter nibbles (4 x 256 bits) is transferred to the periphery readout logic in parallel. Here, the bits of 8 columns are grouped to form a “supercolumn”, serialised and presented at the output with a faster clock (100MHz DDR). The readout of the resulting 32 supercolumns happens in parallel on 32 readout lines. To reduce to a very minimum the dead time between frames the chip features double buffered storage, so a next frame can already be taken while the previous one is being readout. The estimated dead time between frames (needed to perform the buffering and counters reset) is about 1 μs. Moreover, the maximum frame rate can be adjusted using the selectable length of the pixel counter, ranging from 4 bits (lower flux-very high frame rate applications) to 12 bits. In 4 bit mode the frame rate can be up to about 24 Kframes/s. To reduce to a very minimum the dead time between frames the chip features double buffered storage. In 4 bit mode the frame rate can be up to about 24 Kframes/s. The readout architecture is targeting very fast frame rates. For this reason a high level of parallelism is embedded in the chip.