doc.: IEEE 802.15-<doc#> <month year> doc.: IEEE 802.15-<doc#> Oct 2004 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [IEEE 802.15.4b High Rate Alt-PHY proposals - Further Performance Comparison] Date Submitted: [20 Oct, 2004] Source: [Francois Chin] Company: [Institute for Infocomm Research, Singapore] Address: [21 Heng Mui Keng Terrace, Singapore 119613] Voice: [65-68745684] FAX: [65-67768109] E-Mail: [chinfrancois@i2r.a-star.edu.sg] Re: [Response to the call for proposal of IEEE 802.15.4b, Doc Number: 15-04-0239-00-004b] Abstract: [This presentation compares all proposals for the IEEE802.15.4b PHY standard.] Purpose: [Proposal to IEEE 802.15.4b Task Group] Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15. Francois Chin, Institute for Infocomm Research (I2R) <author>, <company>

Oct 2004 Background Main contribution of current doc is to provide further simulation results based on 1000 channel realisation, for the PHY proposals using coherent detection Previous comparison used 100 channel realisation, as in IEEE Doc 15-04-0507-04-004b Performance comparison herein done with {0,1,2} cyclic chip extension {1,2,3} RAKE fingers Francois Chin, Institute for Infocomm Research (I2R)

Oct 2004 Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code Set C8 E16 F31 G16 Description 8-chip for Coh. Chip Despreading Orthogonal 16-DSSS PSSS 16-chip for Coh. Chip Despreading Proposer I2R Helicomm Dr. Wolf & Assoc. Doc # 04-507 04-314 04-121 04-507(new) Sym-Chip mapping Cyclic & Odd Bit Inversion Orthogonal Multi-code Bit/sym 4 15 Chip/Sym 8+1 cyclic extension 16+1 cyclic extension 31+1 cyclic extension Bit/chip 0.44 0.25 ~0.47 ~0.24 Root Sequence 5C N.A. 08B3E375 2F53 Coh. Chip Despreading (CCD) Yes Differential Chip Despreading (DCD) No Source: 15-04-0507-04-004b Francois Chin, Institute for Infocomm Research (I2R)

Comparison Methodology Oct 2004 Comparison Methodology Multipath robustness performance Investigation done with Zero, one and two Cyclic chip(s) extension One, two & three RAKE fingers Bandwidth efficiency (bps / Hz) RF requirement Memory requirement Francois Chin, Institute for Infocomm Research (I2R)

Multipath Realisations Oct 2004 Multipath Realisations 100 Channel Realisations at each RMS Delay Spread Francois Chin, Institute for Infocomm Research (I2R)

Multipath Realisations Oct 2004 Multipath Realisations 100 Channel Realisations at each RMS Delay Spread Francois Chin, Institute for Infocomm Research (I2R)

Proposed Symbol-to-Chip Mapping (8-chip Code Set C8) Oct 2004 Proposed Symbol-to-Chip Mapping (8-chip Code Set C8) Decimal Value Binary Symbol Chip Value 0000 0 1 0 1 1 1 0 0 (Root – 5C) 1 1000 0 0 1 0 1 1 1 0 2 0100 0 0 0 1 0 1 1 1 3 1100 1 0 0 0 1 0 1 1 4 0010 1 1 0 0 0 1 0 1 5 1010 1 1 1 0 0 0 1 0 6 0110 0 1 1 1 0 0 0 1 7 1110 1 0 1 1 1 0 0 0 8 0001 0 0 0 0 1 0 0 1 9 1001 1 0 0 0 0 1 0 0 10 0101 0 1 0 0 0 0 1 0 11 1101 0 0 1 0 0 0 0 1 12 0011 1 0 0 1 0 0 0 0 13 1011 0 1 0 0 1 0 0 0 14 0111 0 0 1 0 0 1 0 0 15 1111 0 0 0 1 0 0 1 0 The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values) Francois Chin, Institute for Infocomm Research (I2R)

Other Root Sequences (8-chip C8 for Coherent Despreading only) Oct 2004 Other Root Sequences (8-chip C8 for Coherent Despreading only) The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 9 18 23 29 33 36 46 58 66 71 72 92 111 113 116 123 132 139 142 144 163 183 184 189 197 209 219 222 226 232 237 246 Francois Chin, Institute for Infocomm Research (I2R)

DSSS Sequence E16 Oct 2004 Source doc.: IEEE 802.15-04-0314-02-004b Decimal Symbol Binary Symbol Chip Values 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 3 1 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 4 0 0 1 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 5 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 1 1 0 6 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 7 0 1 1 1 0 1 0 1 1 1 0 1 0 0 1 0 1 1 0 1 8 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 9 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 10 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 11 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 1 0 1 12 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 13 1 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 14 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 15 1 1 1 1 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 0 Source doc.: IEEE 802.15-04-0314-02-004b Francois Chin, Institute for Infocomm Research (I2R)

PSSS Sequence F31 (15 bit/32 chip) Oct 2004 PSSS Sequence F31 (15 bit/32 chip) Source doc.: IEEE 802.15-04-0121-04-004b No Pre-coding is employed in this simulation Francois Chin, Institute for Infocomm Research (I2R)

Proposed Symbol-to-Chip Mapping (16-chip Code Set G16) Oct 2004 Proposed Symbol-to-Chip Mapping (16-chip Code Set G16) Decimal Value Binary Symbol Chip Value 0000 0 0 1 0 1 1 1 1 0 1 0 1 0 0 1 1 (Root - 2F53) 1 1000 1 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 2 0100 0 0 1 1 0 0 1 0 1 1 1 1 0 1 0 1 3 1100 0 1 0 0 1 1 0 0 1 0 1 1 1 1 0 1 4 0010 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 1 5 1010 1 1 0 1 0 1 0 0 1 1 0 0 1 0 1 1 6 0110 1 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 7 1110 1 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 8 0001 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 9 1001 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 10 0101 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 11 1101 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 12 0011 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 13 1011 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 14 0111 1 0 1 0 0 0 0 0 0 1 1 0 0 1 1 1 15 1111 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 1 The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values) Francois Chin, Institute for Infocomm Research (I2R)

Other Root Sequences (8-chip G16 for Coherent Despreading only) Oct 2004 Other Root Sequences (8-chip G16 for Coherent Despreading only) The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 1915 3566 12115 21038 22715 31238 34297 42820 44497 53420 61969 63620 Francois Chin, Institute for Infocomm Research (I2R)

Multipath Performance (PSSS) Oct 2004 For PSSS (without pre-coding), 2 RAKE fingers + 1 chip extension are required to overcome BER floor Francois Chin, Institute for Infocomm Research (I2R)

Multipath Performance (COBI 16-chip) Oct 2004 For 16-chip COBI Sequence, 2 RAKE + 1 chip extension fingers are required to over BER floor Francois Chin, Institute for Infocomm Research (I2R)

Multipath Performance (COBI 8-chip) Oct 2004 For 8-chip COBI Sequence, 2 RAKE + 1 Chip Extension are required to overcome BER floor Francois Chin, Institute for Infocomm Research (I2R)

Multipath Performance (DSSS) Oct 2004 For DSSS, even 3 RAKE fingers cannot overcome BER floor Francois Chin, Institute for Infocomm Research (I2R)

Coherent Receiver Multipath Performance Oct 2004 1 chip extension is necessary to overcome BER floor due to excessive inter-chip interference due to dense multipath DSSS could not overcome Interchip interference even with 3 RAKE fingers and 2 chip extension For 10-5 BER, Given receiver with 2 RAKE fingers + 1 chip extension, PSSS (31+1 chip) & COBI sequence (16+1 chip) have similar performance, with COBI (8+1 chip) needing ~ 3dB more Francois Chin, Institute for Infocomm Research (I2R)

Coherent Receiver Multipath Performance Oct 2004 Coherent Receiver Multipath Performance General performance comparison: PSSS (31+1 chip) > COBI sequence (16+1 chip) > COBI sequence (8+1 chip) > DSSS Sequence (16 +1 chip) What leads to Multipath robustness? Frequency selectivity leads to Inter-chip interference, and that is the killer…. To overcome, code must have good autocorrelation properties, i.e. low sidelodes Francois Chin, Institute for Infocomm Research (I2R)

How these codes achieve Multipath robustness? Oct 2004 How these codes achieve Multipath robustness? PSSS, uses flexibility in amplitude to achieve zero auto-correlation throughout COBI, maintain constant module, can at best achieve zero auto-correlation within 2 chips from cor. Peak; that is good enough to handle ICI of upto 2 chip periods DSSS, comprising Walsh sequences, has auto-correlation sidelodes COBI 8-chip autocorrelation matrix Francois Chin, Institute for Infocomm Research (I2R)

How these codes achieve Multipath robustness? Oct 2004 How these codes achieve Multipath robustness? COBI 16-chip autocorrelation matrix Francois Chin, Institute for Infocomm Research (I2R)

Multipath Performance Summary (Coherent Chip Despreading) Oct 2004 Multipath Performance Summary (Coherent Chip Despreading) To combat inter-chip interference due to relatively large channel delay spread (RMS delay spread / chip period ~ 0.6, that is 2us for 868MHz band and 0.6us for 915MHz bands), 2 recommendations are: RAKE combining (with 2 fingers) in receiver to combine path diversity; (this does not affect standard) One additional chip extension to the chip sequence to avoid inter-symbol interference (this one does) With the 2 recommendations, under large channel delay spread @ BER = 10-5 (PER ~ 1% @ 127 byte-packet), PSSS (31+1 chip) & COBI sequence (16+1 chip) have similar performance, while COBI (8+1 chip) needing ~ 3dB more Francois Chin, Institute for Infocomm Research (I2R)

Oct 2004 Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code Set C8 E16 F31 G16 Description 8-chip for Coh. Chip Despreading Orthogonal 16-DSSS PSSS 16-chip for Coh. Chip Despreading Proposer I2R Helicomm Dr. Wolf & Assoc. Doc # 04-507 (new) 04-314 04-121 Sym-Chip mapping Cyclic & Odd Bit Inversion Orthogonal Multi-code Bit/sym 4 15 Chip/Sym 8+1 cyclic extension 16+1 cyclic extension 31+1 cyclic extension Bit/chip 0.44 0.25 ~0.47 ~0.24 Multipath performance Better Good Best Memory requirement Low Single sequence High 16 sequence RF linearity requirement Moderate ~ high Note : Red - desirable Francois Chin, Institute for Infocomm Research (I2R)

Coherent Detection Performance (at less channel delay spread) Oct 2004 Coherent Detection Performance (at less channel delay spread) performance comparison: Using 2 RAKE + 1 cyclic chip extension, PSSS (31+1 chip) > COBI sequence (16+1 chip) > COBI sequence (8+1 chip) > DSSS Sequence (16 +1 chip), all within 1 dB Francois Chin, Institute for Infocomm Research (I2R)

Can Non-Coherent Detection be used? Oct 2004 Can Non-Coherent Detection be used? The COBI (+1 chip extension) are designed to give best performance with coherent detection receiver. When the receiver employs non-coherent detection: Yes, COBI sequence (16+1 chip) can handle multipath channels upto RMS delay spread / chip period ~ 0.15 (that is 0.5us for 868MHz band using 600kcps and 0.15us for 915MHz bands using 1Mcps), which normally corresponds to short range indoor environment Yes, COBI sequence (8+1 chip) can handle multipath channels upto RMS delay spread / chip period ~ 0.03 (that is 0.1us for 868MHz band using 600kcps and 0.03us for 915MHz bands using 1Mcps), at even shorter range indoor Francois Chin, Institute for Infocomm Research (I2R)

Code Sequence Recommendations Oct 2004 Code Sequence Recommendations Multipath robustness vs complexity As multipath robustness is vital, and differential chip despreading does not perform well under channels with excessive delay spread, coherent chip despreading with RAKE combining is necessary to ensure coverage in large indoor environment, e.g. industry space One cyclic chip extension is necessary to avoid inter-symbol interference under channels with excessive delay spread 8-chip & 16-chip COBI sequence is recommended for its low RF linearity requirement, high bandwidth efficiency and low memory requirement Nevertheless, Differential chip despreading can also be used in shorter range indoor environment,e.g. residential space, where multipath channel RMS delay spread is small Francois Chin, Institute for Infocomm Research (I2R)