FAULT-TOLERANT TECHNIQUES FOR NANOCOMPUTERS GARIMELLA SUDHEER EE 585: Fault Tolerant Computing Sudheer Fault Tolerant Computing

Fault Tolerant Computing NANOCOMPUTERS A Nanocomputer is a computer whose physical dimensions are microscopic. The proposed Nanometer-Scale devices should eventually permit very large scale of integration of the order of 10^12 devices per chip. ( However this is still at academic level). Current state-of-the-art microprocessors have more than 40 million transistors; by 2012 they could have five billion. Sudheer Fault Tolerant Computing

Fault Tolerant Computing Nanocomputers contd. Nanoelectronic devices are more fragile than the conventional devices, and will be sensitive to external influences such as Radiation related effects High Temperature Electromagnetic Interference Parameter Fluctuations etc. Hence, fault-tolerant architectures will certainly be necessary in order to produce reliable systems that are immune to manufacturing defects and to transient errors. Sudheer Fault Tolerant Computing

Fault Tolerant Computing Introduction The nanometer-sized electronic devices are prone to errors at both Manufacturing and service level. The present day manufacturing failure rate of CMOS is approximately 10^-7 to 10^-6. Failure rate for highly experimental devices such as molecular transistors is currently just below unity. Failure rate cannot be exactly predicted for nanoscale devices but it will be significantly poorer than the present day transistors. Sudheer Fault Tolerant Computing

Fault Tolerant Techniques The proposed fault tolerant techniques for nanocomputers are R- Fold modular redundancy (RMR) Cascaded triple modular redundancy (CTMR) NAND Multiplexing Reconfiguration. The first two techniques are mainly used to correct transient errors. Finally reconfiguration technique is suitable for tackling manufacturing defects. Sudheer Fault Tolerant Computing

R-Fold Modular Redundancy RMR is a generalization of TMR. In Triple modular redundancy three units work in parallel and their outputs are compared with a majority gate. Similarly in RMR R units work in parallel ( where R = 3,5,7,9…..). Sudheer Fault Tolerant Computing

Cascaded Triple Modular Redundancy The TMR process can be repeated by combining three of the TMR ‘units’ with another majority gate to form a ‘second order’ TMR unit with even higher reliability Sudheer Fault Tolerant Computing

Fault Tolerant Computing NAND Multiplexing NAND multiplexing was proposed by Von Neumann 50 years ago. This method is similar to RMR, but instead of majority gate to decide output, the output is carried out on a bundle of wires (Given as Nbundle ). IT has two stages Executive stage. Restorative stage. Sudheer Fault Tolerant Computing

Fault Tolerant Computing Sudheer Fault Tolerant Computing

NAND Multiplexing Contd. The executive stage, performs the basic function of the processing unit in parallel. The restorative stage, reduces the degradation caused by the executive stage and thus acts as a non-linear ‘amplifier’ of the output. The signals to and from units are not carried in single lines but in bundles and the unit is replicated the appropriate number of times. Sudheer Fault Tolerant Computing

NAND Multiplexing Contd. If the inputs and processing units are perfectly reliable then the lines comprising each output should be identically stimulated (1) or unstimulated (0). However, due to errors in the input data as well as errors occurring in the processing of the inputs from faulty devices, not all of the output lines in each output will be identically stimulated. Thus, for multiplexed networks, the final outputs are considered to be 1 if more than (1 −a)Nbundle lines are stimulated and 0 if less than aNbundle lines are stimulated. ( 0<a<0.5, is predefined critical level). Sudheer Fault Tolerant Computing

Fault Tolerant Computing Reconfiguration This technique is used for overcoming Manufacturing defects. Defective devices are assembled in groups to form CLBs (Configurable logic blocks). These CLBS are grouped together to form AFTBS (Atomic fault-tolerant blocks) The AFTBs are then grouped together, NA at a time, to form a cluster which then performs some desired function. Sudheer Fault Tolerant Computing

Fault Tolerant Computing Sudheer Fault Tolerant Computing

Fault Tolerant Computing Results Sudheer Fault Tolerant Computing

Emerging architectures for nanocomputers Sudheer Fault Tolerant Computing

Fault Tolerant Computing Conclusions The implications of these results are that the future usefulness of various nanoelectronic devices may be seriously limited if they cannot be made in large quantities with a high degree of reliability. It is theoretically possible to make very large functional circuits, even with one dead device in ten, but only if the dead devices can be located and the circuit reconfigured to avoid them. Sudheer Fault Tolerant Computing

Current Nanocomputers Spray on Nanocomputer Teramac custom computer which uses Reconfiguration technique. Sudheer Fault Tolerant Computing

Fault Tolerant Computing Referances Fault tolerant techniques for Nanocomputers by K Nikolic, A Sadek and M Forshaw. Fault tolerant techniques for Nanocomputers: NAND Multiplexing By Jie Han and Pieter Jonker. http://www.hpl.hp.com/personal/Bruce_Culbertson/TeramacBib.html Sudheer Fault Tolerant Computing

Fault Tolerant Computing QUESTIONS ?? Sudheer Fault Tolerant Computing