Copyright 2006 - Joanne DeGroat, ECE, OSU Project Step 8 Putting the units together to form a data path consisting of the register set and the ALU. THE HEART OF A PROCESSOR 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU The data path Connect up the register set and the alu ALU need input latches and output drive Control signals coordinated by the testbench which acts like the controller 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

The high level interface – Dashed lines ABUS, BBUS – two 16-bit busses for the transfer of data. Aregload, Aregdriver, Aregno – the control signals for control of the register set’s connection to the A bus. Note that Aregno is of type INTEGER. Bregload, Bregdriver, Bregno – the control signals for control of the register set’s connection to the B bus. Note that Bregno is of type INTEGER. A_ALUload, B_ALUload – control latching the bus value into the input ALU latches A_ALUdrive, B_ALUdrive – control driving the ALU results onto the respective bus Cin – the carry in oper – the operation input to the ALU CNZ – the flag outputs 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU Bus Timing detail Timing is such that sources place their data on the bus as indicated by the drive signal. Drive goes active low at 10 ns Load goes active low at 10 ns Load returns high at 70 ns Drive returns high at 80 ns IN SUMMARY: Sources drive their data onto the bus at 10ns and keep it there until 80ns. Destinations latch the data at 70ns. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Example of an operation Add the contents of register 4 with that of register 6 with results returned to register 6. Cycle 1 – transfer data to ALU Register control signal to drive A bus from register 4 occurs at 10 ns to 80 ns. Register control signal to drive B bus from register 6 occurs at 10 ns to 80 ns. ALU A latch opens at 10 and closes at 70 ns. ALU B latch opens at 10 and closes at 70 ns. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Example of an operation Cycle 2 – complete operation and transfer back. ALU B drive starts at 10 and ends at 80 ns. Register control signal to load B bus to register 6 occurs from 10 ns to 70 ns. Protocol calls for results to be returned during cycle 2 on the B Bus. - what designers decided 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU Other notes Busses are of type std_logic_vector ALU uses type bit Must latch the busses and do a type conversion from std_logic_vector to type bit_vector on input Must use a type bit_vector to type std_logic_vector conversion at output before you drive the value onto the bus. Type conversion functions – to_BitVector, to_StdLogicVector, to_Bit, to_StdLogic 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU Other Notes Register and Busses are 16-bit words ALU is 8 bits. ALU needs to be modified to 16 bits. Why you were told to write the ALU procedures for add, negate, and subtract unconstrained. So modify the ALU to 16 bits. A minor modification. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Other notes from problem description Write a description of the datapath and simulate it. This will be a structural architecture. Use the register set from step 7 Use a modified (to 16 bits) ALU from step 6 Use step 6 as you will need the package for type operations. Busses are of type std_logic_vector and signals such as Cin, C,N,Z are of type std_logic Use type conversion functions as appropriate 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU To turn in Copies of all code The full waveform A part of the waveform zoomed in The listing file VERY IMPORTANT – The entity name of the testbench is simply dp So you will simulate dp There is not a blank area in the file for the code of the package. You can add it or put it in a separate file and submit that to the dropbox. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU