First thoughts on DIF functionality

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Presentation transcript:

First thoughts on DIF functionality data volume: single chip: 20kbits max single sided slab: 1.9Mbits max Lots of controls…. 12-07-2007 CALICE Electronics, CERN

First thoughts on DIF implementation Top-level design diagram includes control signals, to be extended with data transmission signals VFE identification is a major issue: hard-wired (few bits) local ID, or location dependent unique ID? 12-07-2007 CALICE Electronics, CERN

First sketch of possible ECAL DIF TOP VIEW Prototype priority: functionality over form factor Features for debugging and stand-alone operation: large user connector & USB interface We love intermediate boards! for power (pulsing) real-estate to connect to a specific slab interface Intermediate board allows for DIF development without worrying about power pulsing, etc. DIF board with the usual components for flexible development platform Main project will be the ECAL specific firmware 30 layers in 180mm allows for 6mm stack heigth per DIF More efficient space usage by limiting DIF width to 60(80)mm 12-07-2007 CALICE Electronics, CERN

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