COINS‥ a COmpiler INfraStructure COINS helps you to make a new compiler for new language for new processor with new optimization method COINS assists compiler designers educators computer architects

Introduction to COINS written in Java. Slow compilation⇔ easy BUG tracking about 176k lines or 710 source files easy to understand ‥high modularity C and FORTRAN ‥‥ input (Java ‥‥ in progress) SPARC and x86 ‥‥ target (ARM, MIPS, SH4, PowerPC ‥ in progress)

Structure of COINS Language specific analyzer HIR (High-level Intermediate Representation) represents an abstract language keeps source code level info. and suitable for high-level opt. (parallelization , alias analysis) two output paths‥‥LIR and C LIR (Low-level Intermediate Representation) represents an abstract machine has a strictly defined denotational semantics suitable for low-level opt. (SSA, branch, inst. scheduling, SIMD) Re-targetable code generator based on TMD

a + b 1 = a = b + 1; a = b + 1 (assign int <var int a> (add int <var int b> <const int 1>)) a + b 1 = or

a + b 1 = (SET I32 (MEM I32 (FRAME I32 "a.1")) (ADD I32 (MEM I32 (FRAME I32 "b.2")) “a” & “b” : local (INTCONST I32 1))) (SET I32 (MEM I32 (STATIC I32 "a")) (ADD I32 (MEM I32 (STATIC I32 "b")) “a” & “b” : global(INT CONST I32 1))) (assign int <var int a> (add int <var int b> <const int 1>)) a + b 1 = or Visualization

TMD (Target Machine Description) Correspondence between LIR pattern and target machine code pattern LIR→LIR re-writing rules Tmd2Java : iburg-like tree parser generator performing DP matching (for cost). 1408～ ARM 1404 x86 1100 SPARC 1744～ SH4 2807～ PowerPC 1603 MIPS Retargeting costs (lines):

Examples from a TMD (SPARC) ;; Register decl. (def *real-reg-symtab* (SYMTAB (foreach @n (01 23 45 67) ("%l@n" REG I64 4 0)) (foreach @p (i o) (foreach @n (01 23 45) ("%@p@n" REG I64 4 0))) (foreach @gl (g l) (foreach @n (0 1 2 3 4 5 6 7) ("%@gl@n" REG I32 4 0))) (foreach @oi (o i) (foreach @n (0 1 2 3 4 5) ("%@oi@n" REG I32 4 0))) (foreach @n (0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30) ("%f@n" REG F64 8 0)) ("%sp" REG I32 4 0) ("%fp" REG I32 4 0))) ;; Two versions of signed MUL. (foreach (@op @lib) ((MUL .mul) (DIVS .div) (DIVU .udiv) (MODS .rem) (MODU .urem)) (defrule regl (@op I32 regl regl) (cond "!machineOptV8") (regset ($0 *reg-o0-I32*) ($1 *reg-o0-I32*) ($2 *reg-o1-I32*)) (code (call "@lib") (nop)) (clobber (REG I32 "%o1") (REG I32 "%o2")(REG I32 "%o3") (REG I32 "%o4")(REG I32 "%o5")) (cost 10))) ;; V8 MUL instruction (defrule regl (MUL I32 regl rc) (cond "machineOptV8") (code (smul $1 $2 $0)) (cost 1))