Applications of GTX Y. Cao, X. Huang, A.B. Kahng, F. Koushanfar, H. Lu, S. Muddu, D. Stroobandt and D. Sylvester Abstract The GTX (GSRC Technology Extrapolation) system serves as a flexible platform for integration and comparison of various studies, aimed at cali-brating and predicting achievable design in future technology generations. The flexibility of GTX makes it particularly useful for development of new studies that model certain aspects of design and technology, and emulation, comparison, and evaluation of various technology extrapolation methods. In this poster, we highlight the ability of GTX to evaluate the sensitivity of estimation methods to their input parameters and to their implicit modeling choices. Our sensitivity studies for existing models reveal a surprisingly high level of uncertainty inherent in predictions of future CPU timing. In particular, existing cycle time models are extremely sensitive to both modeling choices and to changes in device parameters. We also study tbe effect of new SOI device models and effects of repeater optimization, inductance and signal line shielding. Sensitivity Analyses Goal: investigate sensitivity of existing cycle-time prediction models SUSPENS, BACPAC, Fisher (ITRS) Types of sensitivity Parameter sensitivity (to changes in primary input parameters) Model (rule) sensitivity (to changes in the estimation model itself) Parameter sensitivity of cycle-time predictions Common primary input (PI) parameter base for all models (250nm technology, BACPAC’s default parameter values) Change of a single input parameter value by subtracting/adding 10% of its value, and computation of the resulting clock frequency Simultaneous changes of various parameters (up to 7 together) BACPAC is most robust model (may not be the best!) SUSPENS is very sensitive to parameter changes Everything else * For variations from 3 to 1 and 2 Fanout per gate (25%)* Supply voltage Fisher Logic depth (12%) Supply voltage (7%) BACPAC Dielectric constant (0.2%) Input capacitance of a minimum sized device Logic depth On-resistance of a minimum sized device Rent exponent (41%!) Track utilization factor (routing efficiency) Wiring pitch on layers SUSPENS Rather insensitive (<5%) to Very sensitive (>10%) to Model New Device Models New SOI module (assumes partially-depleted SOI and is based on BSIM3SOI models) Comparison between Bulk Si and SOI floating body effect (changes in Idsat) dynamic delay (due to coupling capacitances between same-layer wires) power comparison: Parameter sensitivity for bulk Si and SOI device models Delay uncertainty for staggered (S) and non-staggered (NS) repeater topologies using bulk and SOI (1.5cm global wire with 4 100X repeaters) (worst case – best case) / nominal delay Repeater intervals and line widths optimized subject to constraints on delay uncertainty and on peak coupling noise 100.00 66.03 56.74 Total power 0.54 0.36 0.12 0.07 Leakage 15.47 10.21 13.54 7.68 Short circuit 1.31 0.86 1.66 0.94 Memory 14.62 9.65 13.98 7.93 Clock distribution 20.22 13.35 20.65 11.71 I/O drivers + pads 3.93 2.60 3.88 2.20 Global interconnects 43.91 28.99 46.18 26.20 Logic + local wires % P (W) Bulk Si SOI GTX: The GSRC Technology Extrapolation System Evaluates the impact of both design and process technology on achievable design and associated design problems. Sets new requirements for CAD tools and methodologies. Allows easy integration, evaluation and comparison of several technology extrapolation efforts. Is based on the concepts of “parameters” (technology description) “rules” (derivation methods) “rule chains” (inference chain) a “derivation engine” (executes rule chain) a “GUI” (represents results, provides user interaction) Sensitivity to rules of other models (model sensitivity) Replacement of one rule of BACPAC / Fisher with a rule (or a set of rules) from another model BACPAC and Fisher are comparable except for a few rules Fisher model shows more variation than BACPAC Differences are larger for local than for global delay We also assessed the effects of clock skew (Takahashi model) and leading-edge interconnect optimizations such as wire sizing, driver and wire sizing, and buffer insertion and wire sizing (IPEM model) Inductance Analysis Comparison of five analytic RC and RLC delay models Non-staggered repeaters Shielding Topologies Optimize cost function = wire pitch x repeater size x number of repeaters Parameters: width of shield and signal wires spacing between signal wires and from signal wires to shield wires Constraints: delay (uncertainty) noise peak Topologies: No shielding (NS) 1 shield (1S) 2 shields (2S) 7.05 2S 7.40 6.00 5.10 1S RLC 6.75 4.60 2.85 NS 7.65 9.25 5.55 RC, 2 pole 9.00 6.25 3.45 RC, 1 pole 8.75 5.75 SF=3 SF=2 SF=1 Shield Model Staggered repeaters Repeater Optimization Repeater sizing Optimizing energy-delay product instead of delay only (Bakoglu) Bakoglu vastly oversizes! Staggering is beneficial Conclusion The example studies shown in this poster were all performed in the technology extrapolation system GTX. These and other examples confirm that the flexible framework afforded by GTX enables useful studies of alternative modeling choices with relatively little effort, as well as open collaboration in the open-source spirit.