RTL Design Methodology Transition from Pseudocode & Interface Lecture 8 RTL Design Methodology Transition from Pseudocode & Interface to a Corresponding Block Diagram

Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 6, FSMD S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 10.2, Design Examples ECE 448 – FPGA and ASIC Design with VHDL

Structure of a Typical Digital System Data Inputs Control & Status Inputs Control Signals Datapath (Execution Unit) Controller (Control Unit) Status Signals Data Outputs Control & Status Outputs

Hardware Design with RTL VHDL Pseudocode Interface Datapath Controller Block diagram Block diagram State diagram or ASM chart VHDL code VHDL code VHDL code

Steps of the Design Process Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller ASM chart of the Controller RTL VHDL code of the Datapath, the Controller, and the Top Unit Testbench of the Datapath, the Controller, and the Top Unit Functional simulation and debugging Synthesis and post-synthesis simulation Implementation and timing simulation Experimental testing

Steps of the Design Process Practiced in Class Today Text description Interface Pseudocode Block diagram of the Datapath Interface with the division into the Datapath and the Controller ASM chart of the Controller RTL VHDL code of the Datapath, the Controller, and the Top Unit Testbench of the Datapath, the Controller, and the Top Unit Functional simulation and debugging Synthesis and post-synthesis simulation Implementation and timing simulation Experimental testing

Statistics example

Circuit Interface n 2 clk reset din go done dout dout_mode Statistics

Pseudocode no_1 = no_2 = no_3 = sum = 0 for i=0 to k-1 do sum = sum + din if din > no_1 then no_3 = no_2 no_2 = no_1 no_1 = din elseif (din > no_2) then no_2 = din elseif (din > no_3) then no_3 = din end if end for avr = sum / k

Interface Table Port Width Meaning clk 1 System clock. reset System reset. din n Input Data. go Signal active high for k clock cycles during which Input Data is read by the circuit. done Signal set to high after the output is ready. dout Output dependent on the dout_mode input. dout_mode 2 Control signal determining value available at the output. 00: avr, 01: no_1, 10: no_2, 11: no_3.

Block diagram of the Datapath din n n n en1 en reset rst n+m clk clk A gt1 n+m no_1 A>B n esum en reset n B rst clk clk 1 s2 sum n+m en2 enc en reset en reset rst rst clk clk clk clk A gt2 no_2 m A>B n+m n n B i 1 s3 >> m = k-1 en3 en reset rst n clk clk A gt3 avr A>B n no_3 zk no_1 no_2 no_3 B n n n dout_mode 00 01 10 11 2 n dout Block diagram of the Datapath

Interface with the division into the Datapath and the Controller dout_mode din clk reset go n 2 gt1 gt2 gt3 Datapath Controller zk en1 en2 en3 esum enc s2 s3 n dout done