Presenter: Jyun-Yan Li On the Generation of Functional Test Programs for the Cache Replacement Logic W. J. Perez H. Universidad del Valle Grupo de Bionanoelectrónica Cali, Colombia Universidad Pedagógica y Tecnológica de Colombia, Grupo Gira Sogamoso, Colombia D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy 2009 Asian Test Symposium

Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high- frequency devices. While the test of the memory array within the cache is usually accomplished resorting to BIST circuitry implementing March test inspired solutions, testing the cache controller logic poses some specific issues, mainly stemming from its limited accessibility. One possible solution consists in letting the processor execute suitable test programs, allowing the detection of possible faults by looking at the results they produce. 2

In this paper we face the issue of generating suitable programs for testing the replacement logic in set-associative caches that implement a deterministic replacement policy. A test program generation approach based on modeling the replacement mechanism as a Finite State Machine (FSM) is proposed. Experimental results with a cache implementing a LRU policy are provided to assess the effectiveness of the method. 3

IC manufacturing cost most at test and validation processor Not enough methodology to cope with all testing issue for cache Cache testing approaches Hardware based Usually modifies initial design in order to support testing procedures Algorithm based March-like program test data cache Require special system feature to write/read main memory when the cache is disabled focusing on testing memory element not cache controller Software-based Self-Test (SBST) depend on effective test program 4

5 SBST Data cache Processor Functional test of processor [7] Functional test of processor [7] A hybrid method for data & instruction controller [9] A hybrid method for data & instruction controller [9] Test cache memory module & control logic On the Generation of Functional Test Programs for the Cache Replacement Logic This paper: Direct mapped data cache [16] Direct mapped data cache [16] Data controller [8] Data controller [8] Determine cache Hit or miss by access cycle which is counter Executing suitable program by ISA instruction and checking the result to detect faults Determine cache Hit or miss by I-IP which observes response and generates error signal

Focus on the data part of cache and replacement mechanism of cache controller Selecting the effective address of every memory access Checking expected results is more complex Not causing produce wrong results, but slowing down its performance Some mechanism able to verify cache hit or miss as expected As cache monitor 6

Build FSM of the replacement mechanism Implementation machine seen as a black box Observing I/O behavior Generate a test sequence for testing replacement mechanism Finding a tour to traverse every edge generating the sequence of addresses to traverse all the transitions 7

Input I n address stored in the n ways of cache set Initial state Some address produce a cache miss for transfer new state Output O Checking hit or miss by the cache monitor State S Permutation of n way which way can be replaced In an n-way set associative, each state has n+1 outgoing transitions n transitions produce a hit 1 transition produces a miss 8

9 s 0 : w 1 w 2 w 3 s 4 : w 3 w 1 w 2 s 2 : w 2 w 1 w 3 t 1 : hit(w 1 ) t 8 : hit(w 3 ) t 7 : hit(w 2 ) t 9 : miss LRU MRU t 15 : hit(w 1 ) t 19 : hit(w 1 ) s 1 : w 1 w 3 w 2 t 10 : hit(w 2 )

How to generate a transition tours Chinese Postman Problem (CPP) Find the shortest tour which every edge is traversed at least once Using in the undirected graph Floyd-Warshall algorithm A sequence of memory accesses that identified the current state indirectly by cache monitor Back to the original state at the end of sequence 1. access address (A n+1 ) to remove address A n which in the way W n 2. read A n again that will replaced A n-1 (in the W n-1 ) and check cache miss/hit 3.read A n-1 again and check miss/hit. Repeat step 3 for all the ways 4. read n-1 addresses which in the way to cause hit and back to the original state 10

11 LRUMRU s 0 : w 1 w 2 w 3 s 4 : w 3 w 1 w 2 s 3 : w 2 w 3 w 1 A 1 : miss A 3 : miss A 2 : miss A 3 : hit(w 2 ) A 2 : hit(w 1 ) A 4 : miss Initial state

12 s 2 : w 2 w 1 w 3 s 5 : w 3 w 2 w 1 s 1 : w 1 w 3 w 2 LRU MRU 1 A 4 : miss A 3 : miss 2 A 2 : hit(w 2 ) 3 Wrong at the Initial state error

How many instructions in the test program Clock cycle for the simulation How much Fault coverage at the stuck-at fault Which kind of the faults Comparing with ? Compare with March C- in the [16] Not compare with reference [8] and [9] 13

LEON2 processor with a 3-way data cache Write through policy Write no-allocate on a write miss LRU replacement Stuck at fault Cache controller: LRU: March C-Proposal Method Instructions (lines) Sizes (byte) Clock cycle217 K571 K Fault coverage (%)89%100%

Present a generic testing method for replacement mechanism of cache controller Based on the FSM model of circuitry and produce a sequence of memory operation to excite the replacement mechanism It can be implementation for n-way and any replacement policy My comment Another method to verify cache controller How to select effective address to excite the controller of instruction cache 15

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