Introduction to Partial Reconfiguration Adam Flynn EEL 4930/5934 4/11/08 4/11/08

Agenda Introduction Definitions and Acronyms Potential Implementations Example Applications Demo

Introduction Full Reconfiguration Partial Reconfiguration (PR)? Bitfile for entire FPGA is loaded onto FPGA Partial Reconfiguration (PR)? Only certain portion(s) of FPGA are reprogrammed Advantages Shorter reconfiguration time Less power Smaller bitfiles Rest of FPGA can remain operational Few applications outlined later

Definitions and Acronyms Partial Reconfiguration Module (PRM) Design module that is swapped in and out on the fly Partial Reconfiguration Region (PRR) Section of FPGA fabric set aside for a PRM. A single PRR can have multiple PRMs defined for it Base Design Static portion of the design – everything that’s not a PRM and remains operational during PR Bus Macro Pre-placed, pre-routed macro that locks routing between PRMs and the base design How PRM communicates with rest of FPGA

Potential Application Module A C PRR B FPGA Base (Static) Region PR Region Bus Macros Apply to what we’ve done so far in class … Modules A, B, C are memory map, register file, controller, etc … PRR is Fibonacci Calculator or Accumulator Can reconfigure FPGA to implement any function Provided function is amenable to standard interface 5

PR Implementation #1 Single Reconfigurable Module Static Configuration\Communication Controller I/O Bus macros Pad BM 3 = Static section controls PRR, provides interface to system Access to I/O must go through bus macro

PR Implementation #2 Module #1 #3 #2 #4 Smallest Reconfigurable Wiring Biggest Configuration\ Communication Controller Module #1 #3 #4 #2

PR Implementation #3 #1 Module #2 Configuration\ Communication Controller

Application A Embedded system where FPGA must constantly communicate with system Mission critical modules can maintain real-time links while the functionality of other portions of the FPGA are reconfigured Not possible with full reconfiguration Reconfiguring PRRs can allow FPGA to … Implement alternate video coding standard Use different radio link protocol/frequency Provide hardware acceleration for several kernels too large to fit onto FPGA simultaneously 9

Application B Fault Tolerance Useful for FPGAs in harsh environments (i.e. space) Configuration bits can become corrupted Adaptable Component-level Protection Level of Fault Tolerance/Protection can be reconfigured See figure for visualization Configuration Scrubbing “Configuration Manager” monitors configuration bits, corrects corrupted bits Component- level Adaptation A B A B L A N K C B A B L A N K B D “sockets” for modules 4× parallel, single no parallel, SCP no parallel, TMR 2× parallel, SCP SIFT – Software-Implemented Fault Tolerance SSCP – Spatial Self-Checking Pair TSCP – Temporal Self-Checking Pair SNMR – Spatial N-Mod Redundancy TNMR – Temporal N-Mod Redundancy ABFT – Algorithm-Based Fault Tolerance

Application C Multipurpose System Design Idea: Create high level design with several PPRs PRRs can be [re]populated as application requirements are defined/change Provides flexibility Does not require designer to anticipate future upgrades Soc example shown Debatable as to whether this is worthwhile

Acknowledgements Chris Conger, Ross Hymel Borrowed heavily from previous presentations

Demo