CSE 140 Lecture 9 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego

Sequential Networks Components F-Fs Specification X Y CLK Combinational CLK A B C D S(t) Components F-Fs Specification Implementation: Excitation Table

Specification Finite State Machine: Circuit: Input Output Relation State Diagram (Transition of States) State Table (Truth Table of Next State and Outputs) Circuit: Logic Diagram Netlist Boolean Expression

Specification Netlist => State Table => State Diagram => Input Output Relation Example 1 with D Flip Flops Example 2 with other Flip Flops

Example 1 with D Flip Flops Q0 Q1 D Q Q’ y D1 D0 CLK y(t) = Q1(t)Q0(t) Q1(t+1) = D1(t) = x(t) + Q0(t) Q0(t+1) = D0(t) = x(t)Q1(t)

Netlist  State Table  State Diagram  Input Output Relation x D1 Q1 Q0 Q D Q’ y Q D Q0 Q1 D0 Q’ CLK y(t) = Q1(t)Q0(t) Q1(t+1) = D1(t) = x(t) + Q0(t) Q0(t+1) = D0(t) = x(t)Q1(t)

Netlist  State Table  State Diagram  Input Output Relation y(t) = Q1(t) Q0(t) Q1(t+1) = D1(t) = x(t) + Q0(t) Q0(t+1) = D0(t) = x(t) Q1(t) State table State Assignment input S0 S1 S2 S3 PS input x=0 x=1 S0, 0 S2, 0 S2, 0 S2, 0 S0, 0 S3, 0 S2, 1 S3, 1 PS x=0 x=1 Let: S0 = 00 S1 = 01 S2 = 10 S3 = 11 0 0 0 1 1 0 1 1 00, 0 10, 0 10, 0 10, 0 00, 0 11, 0 10, 1 11, 1 Q1(t) Q0(t) Q1(t+1) Q0(t+1), y(t) Remake the state table using symbols instead of binary code , e.g. ’00’

Time 1 2 3 4 5 Input - State S0 S2 S3 Output Netlist  State Table  State Diagram  Input Output Relation x/y S1 S2 S3 S0 0,1/0 1/0 0/1 0/0 1/1 S0 S1 S2 S3 PS input x=0 x=1 S0, 0 S2, 0 S2, 0 S2, 0 S0, 0 S3, 0 S2, 1 S3, 1 Example: Output sequence Time 1 2 3 4 5 Input - State S0 S2 S3 Output

Example 2 with T Flip-Flops Q Q’ y Q0 Q1 T0 T1 y(t) = Q1(t)Q0(t) T0(t) = x(t) Q1(t) T1(t) = x(t) + Q0(t)

Logic Diagram => Excitation Table => State Table y(t) = Q1(t)Q0(t) T0(t) = x(t) Q1(t) T1(t) = x(t) + Q0(t) Q0(t+1) = T0(t) Q’0(t)+T’0(t)Q0(t) Q1(t+1) = T1(t) Q’1(t)+T’1(t)Q1(t) Excitation Table: Truth table of the F-F inputs id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y 1 2 3 4 5 6 7 All these forms are equivalent. Given one, we can derive the others.

Excitation Table: iClicker In excitation table, the inputs of the flip flops are used to produce The present state The next state

Excitation Table =>State Table => State Diagram id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y 1 2 3 4 5 6 7 State Assignment S0 00 S1 01 S2 10 S3 11 1/1 PS\Input X=0 X=1 S0 S0,0 S2,0 S1 S3,0 S2 S1,0 S3 S1,1 S0,1 0/0 0/1 All these forms are equivalent. Given one, we can derive the others. S0 S1 S3 1/0 0, 1/0 1/0 S2 0/0

Time 1 2 3 4 5 Input - State S0 S2 S1 S3 Output Netlist  State Table  State Diagram  Input Output Relation PS\Input X=0 X=1 S0 S0,0 S2,0 S1 S3,0 S2 S1,0 S3 S0,1 0/0 S0 S1 S3 S2 1/1 0/1 0, 1/0 1/0 Example: Output sequence Time 1 2 3 4 5 Input - State S0 S2 S1 S3 Output All these forms are equivalent. Given one, we can derive the others.

Implementation State Diagram => State Table => Logic Diagram Excitation Table (Truth Table of the F-F Inputs) Canonical Form: Mealy and Moore Machines Examples Timing

Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. S1 S0 a/0 b/0 b/1 S2

State Diagram => State Table with State Assignment PS\x a b 1 00 01,0 00,0 01 10,0 10 00,1 State Assignment S0: 00 S1: 01 S2: 10 Q1(t+1)Q0(t+1), y a: 0 b: 1

Example 2: State Diagram => State Table => Excitation Table => Netlist id Q1Q0x D1D0 y 000 01 1 001 00 2 010 10 3 011 4 100 5 101 6 110 -- - 7 111 PS\x 1 00 01,0 00,0 01 10,0 10 00,1

Example 2: State Diagram => State Table => Excitation Table => Netlist id Q1Q0x D1D0 y 000 01 1 001 00 2 010 10 3 011 4 100 5 101 6 110 -- - 7 111 0 2 6 4 1 3 7 5 x(t) Q1 0 1 - 1 0 0 - 0 Q0 D1(t): D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x

Example 2: State Diagram => State Table => Excitation Table => Netlist Q’1 Q0 D0 Q Q’0 D x’ Q’ Q1 y x’ D1 Q D Q0 Q’ Q1 x D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x

Example 2: State Diagram => State Table => Excitation Table => Netlist Q Q’ Q1 Q0 D1 D0 x’ x y Q’1 Q’0 iClicker: The relation between the above state diagram and sequential circuit. One to one. One to many Many to one Many to many None of the above

Canonical Form: Mealy and Moore Machines x(t) Combinational Logic y(t) CLK x(t) C2 y(t) x(t) C1 C2 y(t) C1 CLK CLK

Canonical Form: Mealy and Moore Machines Mealy Machine: yi(t) = fi(X(t), S(t)) Moore Machine: yi(t) = fi(S(t)) si(t+1) = gi(X(t), S(t)) x(t) x(t) C1 C2 y(t) C1 C2 y(t) CLK CLK S(t) S(t) Mealy Machine Moore Machine

Finite State Machine Example Traffic light controller Traffic sensors: TA, TB (TRUE when there’s traffic) Lights: LA, LB

FSM Black Box Inputs: CLK, Reset, TA, TB Outputs: LA, LB

FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

FSM State Transition Table PS Inputs NS TA TB S0 X S1 1 S2 S3

State Transition Table PS Inputs NS Q1(t) Q0(t) TA TB Q1(t +1) Q0(t +1) X 1 State Encoding S0 00 S1 01 S2 10 S3 11 Q1(t+1)= Q1(t)Å Q0(t) Q0(t+1)= Q’1(t)Q’0(t)T’A + Q1(t)Q’0(t)T’B

FSM Output Table PS Outputs Q1 Q0 LA1 LA0 LB1 LB0 1 LA1 = Q1 1 Output Encoding green 00 yellow 01 red 10 LA1 = Q1 LA0 = Q’1Q0 LB1 = Q’1 LB0 = Q1Q0

FSM Schematic: State Register

Logic Diagram

FSM Schematic: Output Logic