Status of SOI Pixel Mar. 18, PXD Mtg. Yasuo Arai (KEK)

Slides:

Advertisements

Similar presentations

NxN pixel demonstrator. Time to Digital Converter (2) Tapped delay line –128 cells, 100ps Two hit registers –One per both leading and trailing edge 7.

Advertisements

SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.

Study of the MPPC Performance - contents - Introduction Fundamental properties microscopic laser scan –check variation within a sensor Summary and plans.

SOI Detector (1) Mateusz Baszczyk, Piotr Dorosz, Sebastian Głąb, Wojciech Kucewicz, Łukasz Mik, Maria Sapor (2) Imran Ahmed, Tomasz Fiutowski, Marek Idzik,

Terra-Pixel APS for CALICE Progress meeting 10 th Nov 2005 Jamie Crooks, Microelectronics/RAL.

Striplet option of Super Belle Silicon Vertex Detector Talk at Joint Super B factory workshop, Honolulu 20 April 2005 T.Tsuboyama.

NA62 front end Layout in DM option Jan Kaplon/Pierre Jarron.

NA62 front end architecture and performance Jan Kaplon/Pierre Jarron.

Progress of SOI Pixel Detectors Sep. 9, Yasuo Arai, KEK 1.

SOIPD 2009 SOIPD KEK-LBNL-Padova collaboration. SOIPD 2009 Silicon On Insulator (SOI) detectors SOI-2 (2008) 0.20um OKI FD-SOI technology 128  172 digital.

SOI Pixel Detector : Present Status & Future Plans Super Belle Collb. Mtg Dec. 11, 2008 Yasuo Arai (KEK)

Preliminary Design of Calorimeter Electronics Shudi Gu June 2002.

3D Vertex Detector Status The requirement for complex functionality in a small pixel led us to investigate vertically integrated (3D) processes. Developed.

AIDA design review Davide Braga Steve Thomas ASIC Design Group 9 June 2009.

26/06/2003Nigel Smale University of Oxford Introduction The BeetleMA0 back-up solution. A readout chip that complies to the LHCb read out specifications.

Monolithic Pixels R&D at LBNL Devis Contarato Lawrence Berkeley National Laboratory International Linear Collider Workshop, LCWS 2007 DESY Hamburg, May.

PreAmp with 2nd order highpass and differential output pulser 3rd order lowpass.

ALICE Rad.Tolerant Electronics, 30 Aug 2004Børge Svane Nielsen, NBI1 FMD – Forward Multiplicity Detector ALICE Meeting on Rad. Tolerant Electronics CERN,

Silicon Sensors for Collider Physics from Physics Requirements to Vertex Tracking Detectors Marco Battaglia Lawrence Berkeley National Laboratory, University.

Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science.

1 Development of the input circuit for GOSSIP vertex detector in 0.13 μm CMOS technology. Vladimir Gromov, Ruud Kluit, Harry van der Graaf. NIKHEF, Amsterdam,

VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab *

Super-Belle Vertexing Talk at Super B Factory Workshop Jan T. Tsuboyama (KEK) Super B factory Vertex group Please visit

FPCCD option Yasuhiro Sugimoto 2012/5/24 ILD 1.

Mar. 18, 2009 HAPD ASIC Status Super KEKB Meeting 1 S.Nishida (KEK) S. Nishida HAPD ASIC Status Super KEKB Meeting Mar. 18, 2009 KEK.

Valerio Re, Massimo Manghisoni Università di Bergamo and INFN, Pavia, Italy Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema Fermi National Accelerator Laboratory.

L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.

SIAM M. Despeisse / 29 th January Toward a Gigatracker Front-end - Performance of the NINO LCO and HCO Matthieu Despeisse F. Osmic, S. Tiuraniemi,

Special Focus Session On CMOS MAPS and 3D Silicon R. Yarema On Behalf of Fermilab Pixel Development Group.

LCFI meeting 19 th August 2008 TESTING OF CPR2A Mirek Havranek, Peter Murray, Konstantin Stefanov, Stephen Thomas.

Status of the n-XYTER testing Knut Solvag, Gerd Modzel, Christian Schmidt, Markus Höhl, Andrea Brogna, Ullrich Trunk, Hans-Kristian Soltveit CBM.

RD53 Analog IP blocks WG : developments and plans at CPPM M. Barbero, L. Gallin Martel (LPSC), Dzahini (LPSC), D. Fougeron, R. Gaglione (LAPP), F. Gensolen,

LC Power Distribution & Pulsing Workshop, May 2011 Super-ALTRO Demonstrator Test Results LC Power Distribution & Pulsing Workshop, May nd November.

Pixel detector development: sensor

HCC Derived Clocks. Generated Clocks The HCC generates two clocks from the ePLL 160 MHz clocks and the chip 40 MHz clock, used as a reference: An 80 MHz.

Terra-Pixel APS for CALICE Progress meeting 10 th Nov 2005 Jamie Crooks, Microelectronics/RAL.

Eleuterio SpiritiILC Vertex Workshop, April On pixel sparsification architecture in 130nm STM technology ILC Vertex Workshop April 2008 Villa.

Monolithic Pixel R&D at LBNL M Battaglia UC Berkeley - LBNL Universite' Claude Bernard – IPN Lyon Monolithic Pixel Meeting CERN, November 25, 2008 An R&D.

Aurore Savoy-Navarro 1), Albert Comerma 2), E. Deumens 3), Thanh Hung Pham 1), Rachid Sefri 1) 1) LPNHE-Université Pierre et Marie Curie/IN2P3-CNRS, Fr.

APV25, Clock and Trigger M.Friedl HEPHY Vienna. 2Markus Friedl (HEPHY Vienna)18 Mar 2009 APV25 Please refer to my December 2008 meeting slides for details.

Progress of SOI Pixel sensor R&D T. Tsuboyama (KEK) 1 Ottobre 2014.

CdTe prototype detector testing Anja Schubert The University of Melbourne 9 May 2011 Updates.

PHOTOTUBE SCANNING SETUP AT THE UNIVERSITY OF MARYLAND Doug Roberts U of Maryland, College Park.

1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting London 2008.

GGT-Electronics System design Alexander Kluge CERN-PH/ED April 3, 2006.

M. Manghisoni, L. Ratti Università degli Studi di Pavia INFN Pavia

A General Purpose Charge Readout Chip for TPC Applications

Design of the 64-channel ASIC: status

R&D activity dedicated to the VFE of the Si-W Ecal

ETD meeting Electronic design for the barrel : Front end chip and TDC

PID meeting SCATS Status on front end design

Børge Svane Nielsen/JJG

WP microelectronics and interconnections

Exploring the limits of hybrid pixel detectors with MÖNCH

Christophe Beigbeder PID meeting

R&D status of pixel sensors based on SOI technology

Electronics for the E-CAL physics prototype

Super-Resolution Image Reconstruction

A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS

Phase shifter design for Macro Pixel ASIC

Status of n-XYTER read-out chain at GSI

STT-MRAM Tapeouts: IBM 65nm & IBM 45nm SOI

SVT detector electronics

Yasuhiro Sugimoto KEK 17 R&D status of FPCCD VTX Yasuhiro Sugimoto KEK 17

Silicon pixel detectors and electronics for hybrid photon detectors

Status of SOI Pixel Development

APV25, Clock and Trigger M.Friedl HEPHY Vienna.

The MPPC Study for the GLD Calorimeter Readout

Readout Electronics for Pixel Sensors

Presentation transcript:

Status of SOI Pixel Mar. 18, 2009 @SuperBell PXD Mtg. Yasuo Arai (KEK) yasuo.arai@kek.jp http://rd.kek.jp/project/soi/ 1

Recent Progress Second 0.2um SOI MPW run was submitted on February. 'SVD Amp/Memory' by Piotr Kapusta 'Vertical Integration Test' by LBNL/KEK LBNL Fine Analog SOI Pixel Result

Feb. 2009 Submissin

R&D of Amp/Memory chip for SVD with SOI technology Piotr Kapusta (Institute of Nuclear Physics, Krakow) preamp: output range +- 0.6V, input +-10MIP shaper: peaking time ~20ns pipeline: differential analog memory controlled by shift register fifo: separate analog memory with digital pointers control clk: 40MHz clock power supply: 0, -2.2V

SOI SVD amp for Super Belle 2.4 x 2.4 mm2

6

LDRD-SOI-1 Analog Pixels: Resolution Determine analog pixel spatial resolution by scan with pulsed 1060 nm laser focused on ~5mm spot; Change laser power to simulate different cluster S/N conditions; Reconstruct position using charge center-of-gravity; SOI analog 10 mm pixels demonstrate ~ 1 mm resolution m.i.p. MB et al. to appear on NIM

Use ZyCube m-bump bonding (~5 um pitch) technique. ZyCube + OKI + KEK/LBNL Vertical Integration Use ZyCube m-bump bonding (~5 um pitch) technique. Higher Functionality in each pixel. Increase of material budget is minimum. 8

Vertical Integration 9

Vertical Integration Lower Chip Upper Chip

Summary 2nd SOI MPW run was submitted last month First test circuit for the SupeBelle SVD amp/memory chip was submitted. Position resolution of 1 um is demonstrated by LBNL. We are also developing vertical integration technology which increase the functionality of the pixel. 11