Lecture 14: State Tables, Diagrams, Latches, and Flip Flop EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian March 26, 2015 Department of Electrical Engineering The City College of New York The City University of New York (CUNY)

What we learn so far… Basic Design Combinational Systems (have no memory ) Outputs are only function of current input combination Nothing is known about past events Repeating a sequence of inputs always gives the same output sequence Now – Sequential Systems (have memory) Repeating a sequence of inputs can result in an entirely different output sequence

Sequential Systems Combinational logic + memory devices System outputs Memory updates System inputs Memory contents (data & addresses)

Clocked (Synchronous) System Example of clock signal: T – length of one cycle 1/T – frequency ( 200 MHz -- T = 5 nanoseconds) Leading-edge and Trailing-edge Differences of these two signals?

Definitions of State Tables and Diagrams - 1 A State is a particular set of instructions which will be executed in response to the machine's input. A State Table shows, for each input combination and each state, what the output is and what the next state is. A State Diagram (state graph): a graphical representation of the state table. Timing trace: a set of values for the input and output (and sometimes the state or other variables of the system, as well) at consecutive clock times.

Definitions of State Tables and Diagrams - 2 Present State is the current state stored in memory. Next State is what will be stored in memory after this clock transition. Present output: Moore model -- output depends only on the present state of the system (not the present input). Mealy model – output depends on both the present state and the present input.

State Table and Diagram (Moore model) A system with one input x and one output z such that z=1 if and only if x has been 1 for at least three consecutive clock time. q is the present state: present state output possible clock transitions

State Table and Diagram (Mealy Model) A system with one input x and one output z such that z=1 if and only if x = 1 and has been 1 for at least two consecutive clock time. present state output input 1 Wrong in the textbook

Latches A latch is a binary storage device with feedback. SR NOR latch: (Q´) Set Reset S and R are active high P = (S + Q)´ Q = (R + P)´ If S = 0, R= 0, then P = Q´ & Q = P´ (hold) If S = 1, R= 0, then P = 0 & Q = 1 (store a 1 in the latch, on line Q) If S = 0, R= 1, then P = 1 & Q = 0 (Reset the latch to store a 0 on line Q) If S = 1, R= 1, then P = 0 & Q = 0 (the latch is not operated, forbidden state)

SR NAND Latch indicate active low If = 0, = 1, then Q = 1 (store a 1 in the latch, on line Q) If = 1, = 0, then Q = 0 (Reset the latch to store a 0 on line Q) If = 1, = 1 (hold) If = 0, = 0 (forbidden state)

A Gated Latch Adding a second level of AND gates to a SR latch. Enable signal When gate signal = 0 (disable), the latch remains unchanged (hold). When gate signal = 1 (enable), the latch acts at a SR latch.

Flip Flops A flip flop is a clocked binary storage device that stores either a 0 or a 1. Must have a clock signal (trigger). Leading-edge triggered Trailing-edge triggered Types of Flip Flops: D flip flops SR flip flops T flip flops JK flip flops

D (data or delay) Flip Flops D flip flop performs as its output Q looks like a delay of input D. The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle.

D (data or delay) Flip Flops q* = D The output depends only on the input. The D flip flop behavior table: State and output

A Trailing-edge Triggered D Flip Flop outputs ? ? The changes of D between a clock transition will not change output.

A Leading-edge Triggered D Flip Flop Summary: 1. Q = D (output depends only on the input value at the triggered edges but with a slight delay). 2. The output will not change if the input D changes between a clock period (non triggered edge part)

Announcement HW5 is due today, HW6 is out today, due on 3/31 Read Chapter 6.1, 6.2 Next class (Chapter 6.3): Flip Flops