DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst ITANIUM 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

Why Itanium Processors ? “The best, simplest way to describe the ‘Mission Statement’ for the Itanium Family of microprocessors is: Creation of an architecture that can address future business needs with the best price-performance and flexibility.” - HP/Intel design team - Hewlett Packard / Intel Killer Chip ? Evolution that provides maximum transition and flexibility Add value with minimal risk for the customers 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

Itanium Mission Statement Advances of RISC were no longer at the rate seen in the 1980’s or the 1990’s. Customers continued to ask for greater application performance, due to the following developments: Increased number of users and demand (internet) Higher bandwidth task (streaming) Demand for secure processing (SSL) Larger hardware requirements (Very Large Databases) Support for multi-OS environments (virtual data center, computing as a utility) 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

The Itanium Processor Family New industry standard The “best-of-breed” 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst The Future ? 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst Itanium RAS Features Reliability: built into the processor Availablity Hard Errors: physical change (hardware crash) Soft Errors: random change of a bit => reliablity solves this Software Errors: give the system a place to go to recover from the error and not crash. Serviceability: OLR of I/O cards, CPU, memory, power supplies, ... 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

Processor Technology Evolution EPIC: Performance via Parallelism RISC/OOO: Performance via higher frequency 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

EPIC ( Explicitly Parallel Instruction Computing) EPIC not an evolutionary extension of RISC EPIC = break from RISC-way of doing things RISC & CISC based upon Von Neuman engine (sequential) Out-of-order execution provides limited parallel computing in practice (4 issue units max) More than half the processor power unused each clock cycle Squaring the overhead in RISC (4-8 issue units) 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

RISC / CISC: limited parallelism 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

Itanium: Explicit parallelism 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

Itanium: Explicit parallelism Finding parallelism opportunities is done by the software (compiler). Compiler sees the entire program => finds more opportunities to run items in parallel. Break a program into seperate parallel blocks. 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

Itanium: Explicit parallelism 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

Itanium: Register Set Model Floating Point registers are 82-bit wide. 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst In Summary EPIC is the next enterprise computing architecture, not simply an evolution of RISC Under EPIC the compiler can scan and locate much broader areas to process in parallel, thus allowing for a much larger speed gain. The Itanium processor’s design allows for much larger registers. Registers act as intermediate storage locations for values to reduce the delay in getting instructions and data from memory locations to the processor to speed up processing. These larger registers provide superior performance and accuracy when performing computations involving large, floating-point numbers. 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst Itanium Predication Traditional Architectures: Mispredict penalties can cost up to 40% of performance. Itanium: Predication improves performance by increasing parallelism and avoiding mispredicts. 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst Itanium Speculation Speculation minimizes memory latency 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst

DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst Sources ITANIUM RISING, Breaking through Moore’s Second Law of computing power (Jim Carlson, Jerry Huck), Prentice Hall 2003 ISBN 0-13-046415-5 4 May 2019 DE NAYER INSTITUUT Hogeschool voor Wetenschap & Kunst