Advanced Computer Architecture Lecture 1 Course overview FSM design Lillevik 437s06-l1 University of Portland School of Engineering
Course overview See web site http://lewis.up.edu/egr/lillevik/webs/ Lillevik 437s06-l1 University of Portland School of Engineering
FSM design Assume: synchronous solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik 437s06-l1 University of Portland School of Engineering
FSM architecture Present State NS Decoder Output Inputs Outputs Combo logic ROM MUX Decoder Flip Flops Lillevik 437s06-l1 University of Portland School of Engineering
Next state decoder Combo logic: difficult above 4 inputs ROM MUX n inputs, or address lines 2n data elements Tedious above n = 8, or 256 data elements MUX Fairly easy with simple state dependencies Good choice for n > 8 inputs Lillevik 437s06-l1 University of Portland School of Engineering
Example design Design a 2-bit, Grey code counter with two control signals: enable, up/down Sequence = {0, 1, 3, 2, 0} NOTE: no output decoder required Lillevik 437s06-l1 University of Portland School of Engineering
FSM design Assume: synchronous solution Assume: synchronous solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik 437s06-l1 University of Portland School of Engineering
Determine inputs and outputs? Lillevik 437s06-l1 University of Portland School of Engineering
FSM design Assume: sequential solution Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik 437s06-l1 University of Portland School of Engineering
Create state diagram Lillevik 437s06-l1 University of Portland School of Engineering
FSM design Assume: sequential solution Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik 437s06-l1 University of Portland School of Engineering
Assign adjacent states Lillevik 437s06-l1 University of Portland School of Engineering
FSM design Assume: sequential solution Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik 437s06-l1 University of Portland School of Engineering
Prepare next state table Inputs Present State Next State Outputs U/D Enable Q1 Q0 1 00 01 10 11 Lillevik 437s06-l1 University of Portland School of Engineering
FSM design Assume: sequential solution Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik 437s06-l1 University of Portland School of Engineering
NSD K-maps: Q0’ Q1 U/D 1 3 2 4 5 7 6 8 9 B A C D F E Q0 En 1 3 2 4 5 7 6 8 9 B A C D F E Q0 En Lillevik 437s06-l1 University of Portland School of Engineering
NSD K-maps: Q1’ Q1 U/D 1 3 2 4 5 7 6 8 9 B A C D F E Q0 En 1 3 2 4 5 7 6 8 9 B A C D F E Q0 En Lillevik 437s06-l1 University of Portland School of Engineering
Schematic SOP Implementation 0 - 7 Or gates 8 - f Lillevik 437s06-l1 University of Portland School of Engineering
Count up Lillevik 437s06-l1 University of Portland School of Engineering
Count down Lillevik 437s06-l1 University of Portland School of Engineering
MUX implementation Reduce next state table Implementation For each present state, do K-map on remaining inputs Reduced K-map contains logic expression Implementation Send present state to MUX select lines Place logic function on each input Lillevik 437s06-l1 University of Portland School of Engineering
MUX Example Q1 S0 S1 S3 S2 IN1 1 3 2 4 5 7 6 8 9 B A C D F E Q0 00 01 1 3 2 4 5 7 6 8 9 B A C D F E Q0 00 01 11 10 IN0 00 1 01 1 1 11 10 Lillevik 437s06-l1 University of Portland School of Engineering
MUX Example, continued. Q0 LS153 Q1 1 Gnd 1 Din 2 3 2 3 S Q1,Q0 1 2 3 Q1 IN1·IN0 1 IN1·IN0 Gnd Din IN1·IN0 2 IN1·IN0 IN1·IN0 3 IN1·IN0 S Q1,Q0 Lillevik 437s06-l1 University of Portland School of Engineering
Lillevik 437s06-l1 University of Portland School of Engineering
Determine inputs and outputs Clk Reset Enable U/D Q0 Q1 Four inputs and two outputs Lillevik 437s06-l1 University of Portland School of Engineering
Create state diagram Enable c a b d U/D U/D Enable Enable U/D U/D Reset U/D & U/D NOTE: are anded with Enable Enable Lillevik 437s06-l1 University of Portland School of Engineering
Assign adjacent states Q1 Q0 1 2 3 1 a b 2 3 d c Up states are shown State assignments Lillevik 437s06-l1 University of Portland School of Engineering
Create state diagram Enable 3 1 2 U/D U/D Enable Enable U/D U/D Reset 1 2 U/D U/D Enable U/D U/D Enable U/D U/D U/D U/D Reset U/D & U/D NOTE: are anded with Enable Enable Lillevik 437s06-l1 University of Portland School of Engineering
Prepare next state table Inputs Present State Next State Outputs U/D Enable Q1 Q0 1 00 10 01 11 Count Up Lillevik 437s06-l1 University of Portland School of Engineering
Prepare next state table Inputs Present State Next State Outputs U/D Enable Q1 Q0 1 00 10 01 11 Count Down Lillevik 437s06-l1 University of Portland School of Engineering
NSD K-maps: Q0' 1 1 1 1 1 1 1 1 Q1 U/D 1 3 2 4 5 7 6 8 9 B A C D F E 1 3 2 4 5 7 6 8 9 B A C D F E Q0 En 1 1 1 1 1 1 1 1 Lillevik 437s06-l1 University of Portland School of Engineering
NSD K-maps: Q1' 1 1 1 1 1 1 1 1 Q1 U/D 1 3 2 4 5 7 6 8 9 B A C D F E 1 3 2 4 5 7 6 8 9 B A C D F E Q0 En 1 1 1 1 1 1 1 1 Lillevik 437s06-l1 University of Portland School of Engineering